Lsi Corporation

Xilinx, Inc.

Inphi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Marvell Asia Pte., Ltd.

Credo Technology Group Limited

Astrolink International LLC

Protego Networks, Inc.

Intel Corporation

Stmicroelectronics Gmbh

Dominion Energy Technologies, Inc.

Dominion Resources Services, Inc.

Cisco Technology, Inc.

Astrolink International LLC C/o Lockheed Martin Corporation

Dominion Energy Technologies, Inc. C/o Dominion Resources Services, Inc.

Yu Liao

Haitao Xia

Jamal Riani

Geoffrey Zhang

Hongwei Song

Hongtao Zhang

Haotian Zhang

Sudeep Bhoja

Kun-Yung Chang

Benjamin P Smith

Farshid Rafiee Rad

Jeffrey Paul Grundvig

Richard Rauschmayer

Karthik S Gopalakrishnan

Junqing Phil Sun

Aaron W Buchwald

Jorge Pernillo

Chang-Feng Loi

Mrunmay Talegaonkar

Belal Helal

Praveen Prabha

Junyi Sun

Jingfeng Liu

Partha P Bhattacharya

Zhaoyin D Wu

Nayak Ratnakar Aravind

Marcia Reid Martin

Henrik Fernand Bernheim

Jin Lu

Jerritt Harold Hansell

Dragos Cartina

Andrew Louis Abendschein

ChangFeng Loi

William G Bliss

Haoli Qian

Jihong Ren

Engling Yeo

Jun Xiao

Vassili Kireev

Xun Zhang

Lingyan Sun

Junqing (Phil) Sun

Toan Duc Pham

Wenyi Jin

Edward J D'Avignon

Wen-sin Liew

Ankit Bhargav

Wen-Sin Liew

Jerritt Hansell

Henrik F Bernheim

Fast sampling phase and frequency acquisition suitable for incorporation into various high bandwidth receivers and receiving methods. One illustrative integrated circuit receiver or 'deserializer' design has: a clock circuit that provides a sample clock; an analog to digital converter that samples a receive signal in accordance with the sample clock to provide receive signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock; and a feedback circuit to minimize timing error of the sample clock after the initial frequency offset and initial phase offset have been corrected.

Receivers and method with fast sampling phase and frequency acquisition

A transmitter includes a shift register, a lookup table, and a digital to analog converter. The shift register is configured to receive an input signal and to output delayed copies of the input signal. The lookup table is configured to store compensation values estimated based on the input signal and the delayed copies of the input signal. The digital to analog converter is configured to output a transmit signal based on the input signal and the compensation values. The compensation values are designed to mitigate distortion of the transmit signal from conversion of the input signal to a digital signal.

Method and device for digital compensation of dynamic distortion in high-speed transmitters

Receivers, methods, and cores, can provide decision feedback equalization with efficient burst error correction. An illustrative receiver includes: a decision feedback equalizer that derives symbol decisions from a receive signal; a subtractor that determines an equalization error for each said symbol decision; and a post-processor that operates on the symbol decisions and equalization error to detect and correct symbol decision errors. An illustrative receiving method includes: using a decision feedback equalizer to derive symbol decisions from a filtered receive signal; determining an equalization error for each said symbol decision; and processing the symbol decisions and equalization error to detect and correct symbol decision errors. An illustrative semiconductor intellectual property core generates circuitry for implementing a receiving and method as described above.

Decision feedback equalization with efficient burst error correction

Receivers and receiving methods having maximum likelihood sequence detection with pseudo partial response equalization. One illustrative receiver includes: a feedforward equalizer that produces an equalized receive signal by diminishing a receive signal's intersymbol interference; a decision element that derives initial symbol decisions from samples of the equalized receive signal; and a filter that applies a partial response to the equalized receive signal or to an equalization error signal to produce input for a maximum likelihood sequence detector (MLSD). The MLSD may be a reduced complexity detector that derives a final sequence of symbol decisions by evaluating state metrics only for each initial symbol decision and its competing symbol decision.

Receiver using pseudo partial response maximum likelihood sequence detection

Reduced-complexity maximum likelihood sequence detectors (rMLSD) are disclosed for detecting multibit symbols such as those found in pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM), and phase shift keying (PSK) signal constellations with more than two constellation points. One illustrative digital communications receiver includes: an initial equalizer that derives an initial sequence of symbol decisions from a filtered receive signal, each symbol decision in the initial sequence having a second most likely symbol decision; and a rMLSD that derives a final sequence of symbol decisions by evaluating state metrics only for each symbol decision in the initial sequence and its second most likely symbol decision.

Reduced-complexity maximum likelihood sequence detector suitable for m-ary signaling

The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Clock and data recovery devices with fractional-N PLL

The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

Maximum likelihood error detection for decision feedback equalizers with pam modulation

Maximum likelihood error detection for decision feedback equalizers with PAM modulation

A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.

A system and method for inferring schematic and topological properties of an electrical distribution grid is provided. The system may include Remote Hubs, Subordinate Remotes, a Substation Receiver, and an associated Computing Platform and Concentrator. At least one intelligent edge transmitter, called a Remote Hub Edge Transmitter, may transmit messages on the electrical distribution grid by injecting a modulated current into a power main that supplies an electric meter. The Subordinate Remotes, Remote Hubs, the Substation Receiver, and the associated Computing Platform and Concentrator may contain processing units which execute stored instructions allowing each node in the network to implement methods for organizing the on-grid network and transmitting and receiving messages on the network. The Substation Receiver, Computing Platform, and Concentrator may detect and infer schematic grid location attributes of the network and publish the detected and inferred attributes to other application systems including geospatial information systems.

System and method for inferring schematic and topological properties of an electrical distribution grid

Devices and methods for adjusting operation of a receiver that includes a continuous time linear equalizer, a decision feedback equalizer, and a feed forward equalizer. Operation of the receiver may be controlled by determining whether the receiver is operating in operation region using frequency responses of the feed forward equalizer at a first frequency and a second frequency and using the frequency responses of the decision feedback equalizer at the first frequency and the second frequency. If the operation is outside the frequency, a parameter of the continuous time linear equalizer is adjusted based on the frequency responses of the feed forward equalizer and the decision feedback equalizer.

Adjusting a continuous time linear equalization-based receiver

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Yu Liao