Sk Hynix Memory Solutions Inc.

Etopus Technology Inc.

Link a Media Devices Corporation

Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Broadlogic Network Technologies Inc.

Yu Kou

Lingqi Zeng

Kin Man Ng

Kwok Wah Yeung

Kai Keung Chan

Xiangyu Tang

Danfeng Xu

Jason Bellorado

Marcus Marrow

Rui Cao

Shaohua Yang

Yang Han

Haitao Xia

Bruce Alexander Wilson

Xuebin Wu

Bin-Fan Liu

Vladimir Radionov

Fan Zhang

Shu Li

Zongwang Li

Yingquan Wu

Zheng Wu

Chung-Li Wang

Weimin Zhang

Jianzhong Huang

Abhiram Prabhakar

Qi Zuo

Suharli Tedja

Seongwook Jeong

Xin-Ning Song

Roger Stenerson

Wing Fai Hui

Joseph Garofalo

Tze Yin Cheung

Aditi R Ganesan

A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.

Receiver for high speed communication channel

A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.

Manufacturing testing for LDPC codes

A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.

Timing recovery for digital receiver with interleaved analog-to-digital converters

A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.

Receiver with adjustable reference voltages

A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.

Multi mode viterbi decoder

A receiver for high speed communications. The receiver includes an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock. A finite impulse response filter generates at least one filtered input signal based on the digital input signal. A data decision circuit recovers data based on the filtered input signal. The filtered input signal and the recovered data can be provided to a feedback loop to determine a timing error of the sampling clock, which is then used to generate the sampling clock.

Sampling clock adjustment for an analog to digital converter of a receiver

Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset.

Diversity loop detector with component detector switching

An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.

A plurality of partially-decoded codewords that have been processed at least once by a first and a second error correction decoder is stored. A plurality of metrics associated with how close a corresponding partially-decoded codeword is to being successfully decoded is stored. From the plurality of partially-decoded codewords, a codeword having a metric indicating that that codeword is the closest to being successfully decoded by the first error correction decoder and the second error correction decoder is selected. The selected codeword is output to the first error correction decoder.

Buffer management in a turbo equalization system

Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.

Timing error detector with diversity loop detector decision feedback

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San Jose, CA, United States of America

Yu Kou