Bull S.a.

Yu Jun Qian

Jack Abily

A process and system for flushing high-speed buffers in a serial link used between a mover circuit (4) that executes data move operations and at least two memories through at least two channels (400, 401), the data move operations each being constituted by a move request followed by the return of a response or acknowledgement of the request, cyclically with interlacing, the responses following the same pair of serial channels (400, 401) as the requests for which they constitute the acknowledgements. The process comprises:

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Cergy St Christophe, France

Yu Jun Qian