United Microelectronics Corp.

Food Industry Research and Development Institute

Yu-Ju Liu

Chen-Bin Lin

Sun-Chieh Chien

Chen-Chiu Hsue

Cheng-Hui Chung

Chii-Cherng Liao

Feng-Ming Liu

Yei-Hsiung Lin

Chin-Chun Huang

James Ho

Chin-Chu Yu

Ching-Fen Tan

Sun-Cheih Chien

Disclosed are acid- and bile salt-resistantisolates having the ability to lower cholesterol. The presentisolates or their sub-cultured offspring or mutants derived therefrom can be used in the preparation of various food products, and in the manufacture of medicaments for use in the treatment or prevention of gastrointestinal diseases and for use in lowering serum cholesterol.

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A method of fabricating a MOS transistor. An undoped multi-layer stacked polysilicon structure is formed on a gate oxide layer and then being doped to increase conductivity. After that, the multi-layer stacked polysilicon structure and the gate oxide layer are patterned to form a gate electrode. A source/drain region is formed by ion implantation with the gate electrode as a mask.

Method of fabricating metal-oxide semiconductor transistor

A method of forming metallic capacitor. The method includes forming a lower electrode for forming the capacitor and a metal conductive line over an inter-layer dielectric such that there are gaps between and on the sides of the lower electrode and the metal conductive line. Thereafter, a first oxide layer is formed that fills the gap, and then a second oxide layer is formed over the inter-layer dielectric. The second oxide layer is later patterned to form a cap oxide layer having an opening that exposes a portion of the lower electrode. Subsequently, a thin dielectric layer is formed over the lower electrode and the cap oxide layer. Finally, an upper electrode is formed over the thin dielectric layer filling the opening.

Method for forming metallic capacitor

A process for fabricating a mixed signal integrated circuit on a substrate, wherein the substrate is partially covered with a field oxide layer. An oxide layer is formed over a portion of the substrate, wherein the portion of the substrate is not covered with the field oxide layer. First impurities are implanted into the substrate, wherein the first impurities damage the oxide layer. A buffer layer is formed over the oxide layer. A polysilicon layer is formed over the buffer layer. Second impurities are implanted into the polysilicon layer, wherein the buffer layer prevents the oxide layer form being damaged by the second impurities. The polysilicon layer is etched to remove the polysilicon layer, wherein the buffer layer prevents the oxide layer and the substrate from being etched. The portion of buffer layer and the damaged oxide layer over the substrate are removed. The gate oxide layer is formed over the substrate.

Process for fabricating mixed signal integrated circuit

A method of planarizing an electrical contact region in a silicon substrate uses spin-on-glass or polysilicon as plug material (42) to fill a contact hole (34). A device or doped region (31) is formed at the surface of the substrate (30) and an insulating layer (33) is formed over the substrate so that the entire doped region is covered by the insulating layer. The contact hole is then formed through the insulating layer to expose a portion of the doped region. To increase the conductivity of the doped region through the contact hole, a filler layer of either spin-on-glass or polysilicon, thick enough to substantially fill the contact hole, is formed over the insulating layer. The filler layer is then etched away from the portions around the contact hole by a conventional dry or wet oxide etching process.

Method of contact planarization

A spin-on-glass sandwich layer planarization process where the spin-on-glass layer within the sandwich has been ion implanted through its entire thickness. The spin-on-glass sandwich layer is formed by successive deposition of a silicon oxide layer, followed by a spin-on-glass layer. The spin-on-glass layer is then thermally cured and ion implanted throughout its entire thickness. Various combinations of implanting ions, ion doses and implantation energies are used to implant the spin-on-glass layer. Finally, a second silicon oxide layer is formed upon the surface of the spin-on-glass layer to complete the spin-on-glass sandwich layer.

Spin-on-glass planarization process with ion implantation

A method of removing impurities from the surface of an integrated circuit and forming a uniform thin native oxide layer on the same surface of an integrated circuit is described. A hydrofluoric acid solution, followed by a rinse and spin dry, is often used to remove gate oxide from within an opening etched in a polysilicon layer. The rinsing leaves water spots. Spin drying leaves impurities where water tracks were. An H.sub.2 O.sub.2 cleaning is performed to remove the water spots. After the cleaning, a uniform thin layer of native oxide is formed on the surface of the silicon substrate. A second layer of polysilicon is deposited over this first thin native oxide layer and doped with an implant dosage chosen so that it will go through the uniform native oxide layer. The substrate is annealed to drive in the buried contact. Processing continues to form polysilicon or silicide gate electrodes. Source and drain regions are formed within the openings to the silicon substrate between the gate electrodes. Spacers are formed on the sidewalls of the gate electrodes. An insulating layer is deposited over the surface of the silicon substrate. Contact openings are etched through the insulating layer to the second polysilicon layer and to the silicon substrate. A metal layer is deposited over the insulating layer and filling the openings to the second polysilicon layer and the silicon substrate. The metal layer is patterned, completing the formation of the buried contacts within the integrated circuit.

Growing community of inventors

Hsinchu, Taiwan

Yu-Ju Liu