Samsung Electronics Co., Ltd.

Yu Jin Park

Seog Heon Ham

Jin Ho Seo

Han Vit Yang

Kwi Sung Yoo

Jae Hong Kim

Seung Hyun Lim

Kwang Hyun Lee

Yong Kyun Lim

Kyo Jin Choo

Sin-hwan Lim

Kyoung Min Koh

Min Ho Kwon

Jae Cheol Yun

Ji Hun Shin

Jae Jin Jung

Sung Ho Suh

Han Kook Cho

Chi Ho Hwang

Ji Min Cheon

Min Ji Hwang

Wun Ki Jung

Soon Hwa Kang

An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.

Image sensor and system including the same

An analog-to-digital converter includes a gain amplification unit configured to receive a pixel signal at a first node and to amplify a gain of the pixel signal, a first capacitor connected between the first node and a second node, an amplifier configured to receive and amplify a signal output from the gain amplification unit and the first capacitor, and a conversion circuit configured to convert an output signal of the amplifier to a digital signal based on a reference signal and output the digital signal as a first output signal.

Analog-to-digital converter, image sensor including the same, and image processing device including the image sensor

One embodiment of an analog-to-digital converter includes at least one comparator and a restriction circuit. The comparator has first and second input nodes and a connection node. The connection node is one of an internal node and an output node of the comparator. The restriction circuit is electrically connected to the connection node, and the restriction circuit is configured to restrict a voltage of the connection node.

Analog-to-digital conversion circuit, and image sensor including the same

An apparatus includes an operational amplifier circuit comprising at least one operational amplifier and a feedback circuit coupled between the output terminal and input terminal of the operational amplifier circuit and configured to apply a feedback gain to an output signal at the output of the first operational amplifier. The apparatus further includes a variable compensation capacitor coupled to the output terminal of the operational amplifier circuit and configured to vary a capacitance thereof responsive to the feedback gain.

Amplifier apparatus and methods using variable capacitance dependent on feedback gain

A programmable gain amplifier includes a sampling circuit, a source follower, a first capacitor and an error amplifier. The sampling circuit is configured to perform correlated double sampling on an input signal using a reference voltage. The first capacitor is connected between the sampling circuit and the source follower. The error amplifier is connected between an input terminal of the source follower and an output terminal of the source follower. The error amplifier is configured to reset a voltage of the output terminal of the source follower to the reference voltage during a source follower reset operation.

Programmable gain amplifier and devices including the same

A CDS circuit includes first capacitors; second capacitors; and a switch arrangement which, in response to a switch control signal, connects the first capacitors in series between a pixel signal output node and a ground to compress the pixel signal and connects the second capacitors in series between a ramp signal output node and the ground to compress the ramp signal, or connects the first capacitors in parallel between the pixel signal output node and a first input node of the comparator and connects the second capacitors in parallel between the ramp signal output node and a second input node of the comparator.

Correlated double sampling circuit, method thereof and devices having the same

A correlated double sampling (CDS) circuit includes a correction circuit configured to receive an input pixel signal through a first node via a column line, correct the input pixel signal, and output the corrected pixel signal through a second node; and a comparator including first and second input terminals, the first input terminal being connected to the second node and being configured to receive the corrected pixel signal, and the second input terminal configured to receive a ramp signal, the comparator being configured to compare the corrected pixel signal with the ramp signal and output a comparison signal indicating a result of the comparing, wherein the correction circuit includes, a first capacitor connected between the first and second nodes, and one or more metal lines disposed adjacent to the first capacitor, and wherein at least one other capacitor is formed by the first capacitor and the metal line.

CDS circuit, image sensor including the same, and image processing device including the image sensor

A two-step analog-digital converting circuit includes a comparator, an upper bit counter and a pulse residue conversion unit. The comparator is configured to compare a ramp signal and an input signal, and to output a resulting comparative signal. The upper bit counter is configured to receive the comparative signal and a clock signal, and to output upper bit values corresponding to a first time interval between a generation time point of the ramp signal and a first edge of the clock signal, the first edge of the clock signal immediately preceding a state transition time point of the comparative signal. The pulse residue conversion unit is configured to receive the comparative signal and the clock signal, and to output lower bit values corresponding to a second time interval between the first edge of the clock signal and the state transition time point of the comparative signal.

Two-step analog-digital converting circuit and method

A CDS circuit is provided. The CDS circuit includes a signal compressor which compresses each of a pixel signal and a ramp signal using capacitive dividing and outputs a compressed pixel signal and a compressed ramp signal, and a comparator which compares the compressed pixel signal with the compressed ramp signal and outputs a comparative signal corresponding to a comparison result.

An analog-to-digital converter including a comparator configured to compare a pixel signal received at a first input terminal of the comparator with a ramp signal received at a second input terminal of the comparator and generate a comparison signal as a result of the comparison; and a ramp signal supply circuit configured to provide the ramp signal to the comparator, wherein the ramp signal supply circuit generates a first signal as part of the ramp signal in response to the comparison signal and a first clock signal being received at the ramp signal supply circuit, wherein a slope of the first signal sequentially changes until the comparison signal makes a transition from one logic level to another and, after the transition, the ramp signal supply circuit generates a second signal as part of the ramp signal, wherein a slope of the second signal sequentially changes, wherein the slope of the second signal is opposite the slope of the first signal.

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Seoul, South Korea

Yu Jin Park