Intel Corporation

Yu-Jin Chen

Van H Le

Abhishek A Sharma

Brian S Doyle

Matthew V Metz

Prashant Majhi

Kaan Oguz

Charles C Kuo

Bernhard Sell

Oleg Golonzka

Christopher J Wiegand

Elliot Tan

Travis W LaJoie

Pei-Hua Wang

Urusa Alaan

Justin R Weber

Justin Brockman

Angeline Smith

Tofizur Rahman

Arnab Sen Gupta

Daniel Ouellette

Juan G Alzate Vinasco

Juan G Alzate-Vinasco

Andrew Smith

James Pellegren

Kimberly L Pierce

Aaron Littlejohn

Tanmoy Pramanik

Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

Compositional engineering of Schottky diode

Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.

Memory architecture with shared bitline at back-end-of-line

A memory device includes a first electrode, a second electrode and a magnetic tunnel junction (MTJ) between the first electrode and the second electrode. The MTJ includes a fixed magnet, a free magnet and a tunnel barrier between the fixed magnet and the free magnet. The MTJ further includes a conductive layer between the free magnet and the second electrode, the conductive layer having a metallic dopant, where the metallic dopant has a concentration that increase with distance from an interface between the free magnet and the conductive layer. A capping layer is between the conductive layer and the second electrode.

Magnetic memory devices and methods of fabrication

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Hillsboro, OR, United States of America

Yu-Jin Chen