Unisantis Electronics Singapore Pte. Ltd.

Yu Jiang

Fujio Masuoka

Hiroki Nakamura

Shintaro Arai

Yisuo Li

Tomohiko Kudo

Xiang Li

Navab Singh

Zhixian Chen

Vladimir Bliznetsov

Kavitha Devi Buddharaju

Nansheng Shen

King-Jien Chui

The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.

Surrounding gate transistor (SGT) structure

The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.

Surround gate CMOS semiconductor device

Growing community of inventors

Tokyo, Japan

Yu Jiang