Taiwan Semiconductor Manufacturing Comp. Ltd.

National Sun Yat-sen University of Kaohsiung

Yu-Jen Wang

Dian-Hau Chen

Liang-Wei Wang

Dun-Nian Yaung

Yen-Ming Chen

Chun-Yuan Chen

Shyh-Fann Ting

Hsiao-Hui Tseng

Yen-Ting Chiang

Chen-Chiu Huang

Chih-Chuan Su

Jen-Cheng Liu

Ching-Chun Wang

Jhy-Jyi Sze

Sheng-Chan Li

Tzu-Jui Wang

Wei Chuang Wu

Wei-Chih Wen

Tsung-Chieh Hsiao

Hung-Chao Kao

Po-Sheng Lu

Yuichiro Yamashita

Chih-Hsin Yang

Chih-Pin Chiu

Tzu-Ting Liu

Ren-Yi Huang

Yu-Jan Lo

In a method of manufacturing a semiconductor device including a magnetic random access memory (MRAM) cell, a first layer made of a conductive material is formed over a substrate. A second layer for a magnetic tunnel junction (MTJ) stack is formed over the first conductive layer. A third layer is formed over the second layer. A first hard mask pattern is formed by patterning the third layer. The MTJ stack is formed by patterning the second layer by an etching operation using the first hard mask pattern as an etching mask. The etching operation stops at the first layer. A sidewall insulating layer is formed over the MTJ stack. After the sidewall insulating layer is formed, a bottom electrode is formed by patterning the first layer to form the MRAM cell including the bottom electrode, the MTj stack and the first hard mask pattern as an upper electrode.

Magnetic random access memory and manufacturing method thereof

A semiconductor memory structure includes bottom electrodes formed over a substrate. The structure also includes first magnetic tunneling junction (MTJ) elements formed over the bottom electrodes in a first region and a second region of the substrate. The structure also includes second MTJ elements formed over the first MTJ elements in the first region and the second region. The structure also includes top electrodes formed over the second MTJ elements. The first MTJ elements in the first region are narrower than the second MTJ elements in the first region, and the second MTJ elements in the second region are narrower than the first MTJ elements in the second region.

Semiconductor memory structure and method for forming the semiconductor memory structure

A method for forming a semiconductor memory structure includes forming an MTJ stack over a substrate. The method also includes etching the MTJ stack to form an MTJ device. The method also includes depositing a metal layer over a top surface and sidewalls of the MTJ device. The method also includes oxidizing the metal layer to form an oxidized metal layer. The method also includes depositing a cap layer over the oxidized metal layer. The method also includes oxidizing the cap layer to form an oxidized cap layer. The method also includes removing an un-oxidized portion of the cap layer.

A force sensing device is mounted on a tool to sense force, particularly quasi-static and static forces. The force sensing device includes at least one a sensor. A piezoelectric element in the sensor includes a driving portion and a sensing portion. A first voltage is input to the driving portion to generate a vibration in the piezoelectric element and a second voltage in response to the vibration is output from the sensing portion. The second voltage output from the sensing portion is changed as the vibration in the piezoelectric element is suppressed by an external force acting on the force sensing device so variation of the second voltage can be used to measure the external force.

Force sensing device and sensor and piezoelectric element thereof

The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.

Extra doped region for back-side deep trench isolation

A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.

Semiconductor structure

A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.

Structure and method for MRAM devices

Growing community of inventors

Kaohsiung, Taiwan

Yu-Jen Wang