Taiwan Semiconductor Manufacturing Comp. Ltd.

Headway Technologies, Incorporated

Industrial Technology Research Institute

National Yang Ming Chiao Tung University

Coopervision International Limited

Mstar Semiconductor, Inc.

Hycon Technology Corporation

Mediatek Corporation

Meta Platforms Technologies, LLC

Cameo Communications, Inc.

Tsinghua University

National Sun Yat-Sen University of Kaohsiung

Magic Technologies, Inc.

Advanced Comm. Engineering Solution Co., Ltd.

Pang Chih Industrial Co., Ltd.

Yu-Jen Wang

Dongna Shen

Yi Yang

Ru-Ying Tong

Guenole Jan

Vignesh Sundar

Sahil Patel

Shyh-Fann Ting

Jesmin Haq

Ching-Chun Wang

Jhy-Jyi Sze

Yen-Ting Chiang

Dun-Nian Yaung

Chun-Yuan Chen

Hsiao-Hui Tseng

Chun-Jung Lin

Wei Chuang Wu

Yi-Hsin Lin

Chia-Shiung Tsai

Witold Kula

Denny Tang

Zhongjian Teng

Chung-De Chen

Luc Thomas

Jen-Cheng Liu

Yuichiro Yamashita

Shine Chien Chung

Tzu-Jui Wang

Tom Zhong

Ya-Chen Kao

Huanlong Liu

Pin Chang

Robert Beach

Tao-Wen Chung

Chien-Shien Yeh

Hsu-Chen Cheng

Yeur-Luen Tu

Po-Kang Wang

Hsing-Lien Lin

Sheng-Chan Li

Yen-Chang Chu

Hung-Sen Wang

Yao-Hui Lee

Hung-Chun Lin

Keyu Pi

Jhon Jhy Liaw

Chen-Jong Wang

Yi-Cheng Chen

Chih-Huang Lai

Chih-Ta Wu

Ming-Chieh Chou

Chun-Ming Su

Chung Chien Wang

Hung-Chung Li

Chien Li

Hideaki Fukuzawa

Cheng-Yuan Tsai

Chern-Yow Hsu

Cheng-Hsien Chou

Chi-Hsin Lo

Yuan-Hung Liu

Jian Zhu

Yuan-Jen Lee

Wen-Chin Lin

Jodi Mari Iwata

Chung-Yi Chen

Ming-Syuan Chen

Han-Wei Su

Tzu-Hsiang Chen

I-Nan Chen

Shyang-Jye Chang

Wei-Chuang Wu

Xinyu Zhu

Tai-Feng Wu

Chao-Hsiung Wang

Chulwoo Oh

Lan-Lin Chao

Feng-Jia Shiu

Yun-Han Lee

Chia-Lin Chen

Hung-Shan Chen

Ting-Wei Huang

Ci-Ling Pan

Ru Ying Tong

Rao Annapragada

Wen-Cheng Chen

Linghui Rao

Hui-Min David Wang

Li-Chi Pan

Shih-Hao Wang

Ching-Chang Chen

Wen Chin Lin

Chin-Horng Wang

Chan-Shan Yang

Ming-Chih Tsai

Ming-Te Liu

Shenglin Ye

Scott Jen

Ming-Chieh Tsai

Anup Kumar Sahoo

A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance×area (RA) product than RAfor an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1<RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.

Dual magnetic tunnel junction devices for magnetic random access memory (MRAM)

A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug.

Sub 60nm etchless MRAM devices by ion beam etching fabricated T-shaped bottom electrode

A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The uppermost seed layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is one or more of Ta, TaN, Zr, ZrN, Nb, NbN, Mo, MON, TIN, W, WN, and Ru. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited.

Multilayer structure for reducing film roughness in magnetic devices

A liquid crystal display (LCD) system for a head mounted display includes an LCD panel and a backlight unit. The LCD panel includes a color filter on array (COA) configuration. The backlight unit includes a light adjustment layer to adjust at least one characteristic of illumination light from a light source to tune the illumination light for enlarging an emission cone of display light.

Backlight unit and color filter on array configuration for a liquid crystal display

A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.

Etching and encapsulation scheme for magnetic tunnel junction fabrication

A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.

Self-aligned encapsulation hard mask to separate physically under-etched MTJ cells to reduce conductive re-deposition

An optical subassembly for switchably focusing or redirecting a light beam may include a polarization element having a polarization-selective beam redirection/focusing property, a first switchable polarization rotator upstream of the polarization element, and a second switchable polarization rotator downstream of the polarization element. A polarizer may be provided immediately downstream of the second switchable polarization rotator. The first and second switchable polarization rotators may be operated in counterphase, so as to mutually offset dependence of angle and wavelength characteristics of the polarization rotators on the switching state of the polarization rotators.

Switchable polarization component

A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Under-cut via electrode for sub 60nm etchless MRAM devices by decoupling the via etch process

An ultra-large height top electrode for MRAM is achieved by employing a novel thin metal/thick dielectric/thick metal hybrid hard mask stack. Etching parameters are chosen to etch the dielectric quickly but to have an extremely low etch rate on the metals above and underneath. Because of the protection of the large thickness of the dielectric layer, the ultra-large height metal hard mask is etched with high integrity, eventually making a large height top electrode possible.

Metal/dielectric/metal hybrid hard mask to define ultra-large height top electrode for sub 60nm MRAM devices

A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a NO:silane flow rate ratio of at least 1:1 but less than 15:1. A NO plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Silicon oxynitride based encapsulation layer for magnetic tunnel junctions

A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.

Multiply spin-coated ultra-thick hybrid hard mask for sub 60nm MRAM devices

A dual magnetic tunnel junction (DMTJ) is disclosed with a PL/TB/free layer/TB/PL/capping layer configuration wherein a first tunnel barrier (TB) has a substantially lower resistance x area (RA) product than RAfor an overlying second tunnel barrier (TB) to provide an acceptable net magnetoresistive ratio (DRR). Moreover, magnetizations in first and second pinned layers, PLand PL, respectively, are aligned antiparallel to enable a lower critical switching current than when in a parallel alignment. An oxide capping layer having a RAis formed on PLto provide higher PLstability. The condition RA<RAand RA<RAis achieved when TBand the oxide capping layer have one or both of a smaller thickness and a lower oxidation state than TB, are comprised of conductive (metal) channels in a metal oxide or metal oxynitride matrix, or are comprised of a doped metal oxide or doped metal oxynitride layer.

Dual magnetic tunnel junction (DMTJ) stack design

A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a free layer (FL) has a first interface with a MgO tunnel barrier, a second interface with a Mo or W Hk enhancing layer, and is comprised of FeCoBwherein x is 66-80, y is 5-9, z is 15-28, and (x+y+z)=100 to simultaneously provide a magnetoresistive ratio >100%, resistance x area product <5 ohm/□m, switching voltage <0.15V (direct current), and sufficient Hk to ensure thermal stability to 400° C. annealing. The FL may further comprise one or more M elements such as O or N to give (FeCoB)Mwhere w is >90 atomic %. Alternatively, the FL is a trilayer with a FeB layer contacting MgO to induce Hk at the first interface, a middle FeCoB layer for enhanced magnetoresistive ratio, and a Fe or FeB layer adjoining the Hk enhancing layer to increase thermal stability.

Free layer structure in magnetic random access memory (MRAM) for Mo or W perpendicular magnetic anisotropy (PMA) enhancing layer

A magnetic tunneling junction (MTJ) structure comprises a pinned layer on a bottom electrode. a barrier layer on the pinned layer, wherein a second metal re-deposition layer is on sidewalls of the barrier layer and the pinned layer, a free layer on the barrier layer wherein the free layer has a first width smaller than a second width of the pinned layer, a top electrode on the free layer having a same first width as the free layer wherein a first metal re-deposition layer is on sidewalls of the free layer and top electrode, and dielectric spacers on sidewalls of the free layer and top electrode covering the first metal re-deposition layer wherein the free layer and the top electrode together with the dielectric spacers have a same the second width as the pinned layer wherein the dielectric spacers prevent shorting between the first and second metal re-deposition layers.

Highly physical ion resistive spacer to define chemical damage free sub 60nm MRAM devices

A conductive via layer is deposited on a bottom electrode, then patterned and trimmed to form a sub 20 nm conductive via on the bottom electrode. The conductive via is encapsulated with a first dielectric layer, which is planarized to expose a top surface of the conductive via. A MTJ stack is deposited on the encapsulated conductive via wherein the MTJ stack comprises at least a pinned layer, a barrier layer, and a free layer. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 30 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layer but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.

Highly physical etch resistive photoresist mask to define large height sub 30nm via and metal hard mask for MRAM devices

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San Jose, CA, United States of America

Yu-Jen Wang