Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Jen Chien

Chin-Szu Lee

Szu-Hua Wu

Jung-Tang Wu

Shiu-Ko JangJian

Phil Sun

Yao-Shien Huang

Wan-Ting Huang

Chi-Hung Liao

Han-Ting Tsai

Chia-Hung Tsai

Meng-Yu Wu

Jui-Hung Ho

Wu Meng Yu

I-Pin Chin

A magnetic shield reduces external noise in a chamber including a target and at least one electromagnet for copper physical vapor deposition (PVD). The shield may have a thickness in a range from approximately 0.1 mm to approximately 10 mm to provide sufficient protection from radio frequency and other electromagnetic signals. As a result, copper atoms in the chamber undergo less re-direction from external noise. Additionally, even when hardware failure occurs during PVD (e.g., an electromagnet malfunctions, a wafer stage is not level, and/or a flow optimizer induces too much shift, among other examples), the copper atoms are less susceptible to small re-directions from external noise. As a result, back end of line (BEOL) and/or middle end of line (MEOL) conductive structures are formed in a more uniform manner, which increases conductivity and improves lifetime of an electronic device including the BEOL and/or MEOL conductive structures.

Semiconductor tool for copper deposition

A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.

Method for improving surface of semiconductor device

A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

Method of manufacturing MRAM device with enhanced etch control

A method of forming a memory device includes forming a dielectric structure over a wafer. A bottom electrode via is formed in the dielectric structure. A plasma deposition process is performed to deposit a bottom electrode layer over the bottom electrode via and performing the plasma deposition process includes off-axis rotating a magnet over the wafer to control plasma of the plasma deposition process. A memory material layer and a top electrode layer are formed over the bottom electrode layer. The bottom electrode layer, the memory material layer, and the top electrode layer are patterned to respectively form a bottom electrode, a memory layer, and a top electrode.

Method of forming memory device with physical vapor deposition system

A method of manufacturing a semiconductor device includes: providing a substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

MRAM fabrication and device

An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio.

Growing community of inventors

Taipei, Taiwan

Yu-Jen Chien