Mentor Graphics Corporation

Siemens Industry Software Gmbh

Other

Inluxe LLC

Yu Jane Huang

Wu-Tung Cheng

Ruifeng Guo

Janusz Rajski

Manish Sharma

Liyang Lai

Nagesh Tamarapalli

Kun-Han Tsai

Szczepan Urban

Mark A Kassab

Robert Brady Benware

Huaxing Tang

Jakub Janicki

Sylwester Milewski

Xiaoxin Fan

Randy Klingenberg

Nilanjan Mukherjee

Yu Hu

Shi-Yu Huang

Gaurav Veda

Ting-Pu Tai

Jing Ye

Mason Chern

Jerzy Tyszer

Xijiang Lin

Martin Keim

Paul J Reuter

Christopher W Schuermyer

Ronald Press

Yahya M Z Mustafa

Etienne Racine

Sudhakar Mannapuram Reddy

Jay Babak Jahangiri

Chien-Chung Tsai

Omer Ghazi Samman

Jeffrey Mayer

Kuang Chou Huang

A multi-functional coaster for a cup or other vessel includes a base upon which the vessel can rest upside down, and a decorative body extending away from the base. The decorative body has at least a first electrically powered signal emitter, which preferably include a light emitter and a sound emitter. The decorative body and/or base can also include a fragrance emitter.

Multi-function cup coaster

Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.

Input data compression for machine learning-based chain diagnosis

The operational mode information and the hold-toggle pattern for a flexible isometric test compression system may be determined based on the plurality of test cubes generated for a subset of the targeted faults, the predetermined size and toggle rate for the hold-toggle pattern, and the predetermined maximum number of device inputs for full-toggle scan chains. The operational mode information comprising information of the full-toggle scan chains may be determined based on reduced toggle ranges first and the hold-toggle pattern may then be determined using a relaxation method. Alternatively, the hold-toggle pattern and the full-toggle scan chains may be determined incrementally together.

Isometric control data generation for test compression

A circuit comprises a plurality of scan chains. The plurality of scan chains comprises bidirectional scan cells. Each of the bidirectional scan cells comprises two serial input-output ports serving as either a serial data input port or a serial data output port based on a control signal. Each of the plurality of scan chains is configured to perform a shift operation in either a first direction or a second direction based on the control signal. The first direction is opposite to the second direction.

Bidirectional scan cells for single-path reversible scan chains

Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine observed failing bit patterns. Bit-reduction is performed on the observed failing bit patterns to construct first training samples. Using the first training samples, first-level machine-learning models are trained. Affine scan cell groups are identified. Second training samples are prepared for each of the affine scan cell groups by performing bit-filtering on a subset of the observed failing bit patterns associated with the faults being injected at scan cells in the each of the affine scan cell groups. Using the second training samples, second-level machine-learning models are trained. The first-level and second-level machine learning models can be applied in a multi-stage machine learning-based chain diagnosis process.

Multi-stage machine learning-based chain diagnosis

A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.

Layout-friendly test pattern decompressor

A circuit comprises a scan chain comprising one or more multi-bit flip-flops, a plurality of multiplexers, and new scan enable signal generation circuitry. Each of the plurality of multiplexers is associated with a particular bit of the one or more multi-bit flip-flops with an output of the each of the plurality of multiplexers coupled to a data input of the particular bit, which is configured to select, based on a scan direction control signal, between an input signal from functional circuitry of the circuit and an input signal from a data output of a bit of the scan chain immediately following the particular bit in a normal scan shift direction. The new scan enable signal generation circuitry is configured to generate a new scan enable signal for the one or more multi-bit flip-flops based on the scan direction control signal and a scan enable signal for the scan chain.

Reversible multi-bit scan cell-based scan chains for improving chain diagnostic resolution

A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.

Flexible isometric decompressor architecture for test compression

This application discloses a computing system implementing an automatic test pattern generation tool can generate test patterns to apply to a reversible scan chain in an integrated circuit. The reversible scan chain can be configured to serially load and unload the test patterns in multiple directions to generate test responses. The computing system can implement a defect diagnosis tool to detect a presence of a suspected defect associated with the reversible scan chain based on the test responses, identify which of the multiple directions used to load and unload the test patterns corresponds to the suspected defect in the reversible scan chain based on the test responses, and determine a portion of the integrated circuit to inspect for a manufacturing fault corresponding to the suspected defect based, at least in part, on the identification of which of the multiple directions corresponds to the suspected defect in the reversible scan chain.

Diagnostic resolution enhancement with reversible scan chains

A test pattern is shifted into scan chains in a circuit in a first direction. The scan cells on each of the scan chains are further coupled to corresponding scan cells on two other scan chains in the scan chains such that data bits stored in the scan cells can be shifted circularly in a second direction orthogonal to the first direction based on a control signal. The loaded test pattern is then shifted in the second direction for a number of clock cycles equal to the number of the scan chains. The test pattern is then shifted in the first direction out of the scan chains to generate a chain test result. Faulty scan cell candidates on faulty scan chains may be determined based on part of the chain test result for one of good scan chains.

Chain testing and diagnosis using two-dimensional scan architecture

A circuit comprises a plurality of scan chains configured to perform scan shifting in two opposite directions and a register configured to store a first signal. The first signal determines whether the plurality of scan chains operate in a first mode or a second mode. The plurality of scan chains operating in the first mode is configured to perform, based on a second signal, either scan shifting in a first direction in the two opposite directions or scan capturing during a test; the plurality of scan chains operating in the second mode is configured to perform, based on the second signal, scan shifting in the first direction or a second direction in the two opposite directions.

Low pin count reversible scan architecture

A system and method for performing scan chain testing is disclosed. Scan cells, in the form of scan chains, are inserted into circuit designs for testing those circuit designs. The integrity of the scan chains is checked for defects before testing the circuit under test. In order to do so, various scan chain patterns, including one or both of U-turn and Z-turn patterns, are used in order to generate scan chain test data. The scan chain test data is analyzed in order to identify one or both of a type of defect (e.g., a timing fault, stuck-at fault, etc.) or a location of the defect. Further, the scan chain testing is performed using chain patterns with adaptive length.

Optimized scan chain diagnostic pattern generation for reversible scan architecture

One, two, or three test pattern generation and encoding processes are performed for a circuit design to generate compressed test patterns for one or two input channel numbers. The one, two, or three test pattern generation and encoding processes are configured to minimize active input channels for each of the compressed test patterns. A test pattern count for each of a plurality of input channel numbers is determined based on the compressed test patterns for the one or two input channel numbers, a number of active input channels for each of the compressed test patterns, and an assumption of similar input data volumes for different numbers of input channels. The test pattern count information can be employed to determine an optimal number of input channels for a test decompressor.

Prediction of test pattern counts for scan configuration determination

Constant-output-value gates and buffer gates are determined for gates in a circuit design based on a hold-toggle pattern. The hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles one or more scan chains receive bits based on corresponding bits of a test pattern or same bits as bits of previous shift clock cycles during a shift operation. Activation probabilities and observation probabilities are then determined for circuit nodes of the circuit design based at least in part on the constant-output-value gates and the buffer gates. Finally, test patterns are generated based on the activation probabilities and the observation probabilities.

Test generation using testability-based guidance

A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of '1' and a specified value of '0' for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.

Growing community of inventors

Beverly Hills, CA, United States of America

Yu Jane Huang