Industrial Technology Research Institute

Yu-Hui Lin

Chih-Sheng Lin

Jian-Wei Su

Tuo-Hung Hou

Sih-Han Li

Fu-Cheng Tsai

Yi-Chun Lin

Chih-Ming Lai

Chih-Tang Chang

Syuan-Yi Chen

Ying-Chieh Lei

I-Ta Tsai

Cheng-Yu Wu

Channing Chang

According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

Memory circuit with sense amplifier calibration mechanism

A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Computing in memory cell

A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values. The comparator compares the accumulated data weight value with the reference value(s) to generate a data weight state.

Memory device and data weight state determining method for in-memory computation

A driving assistant method for an electric vehicle is provided with the following steps. When the electric vehicle is started up, a battery energy safe driving region is calculated and displayed. The battery energy safe driving region is updated dynamically according to vehicle information. The vehicle information includes battery information of the electric vehicle.

Driving assistant method and system for electric vehicle

An exceptional road-condition warning device, system and method for a vehicle are provided. The system includes an information processing device and a display device. The display device provides real-time and advance warning information to a driver of the vehicle. The system may notice the driver and passenger in advance to respond to an exceptional road condition before the vehicle approaches the occurring place of the road condition through a back-end cooperative self-learning mechanism. The back-end cooperative self-learning mechanism may collect the exceptional road conditions from different vehicles and update the database automatically to maintain the accuracy. The back-end cooperative self-learning mechanism further shares the information stored in the database with the databases installed in the vehicles by a bidirectional communication manner to update the information inside the database of the vehicles for the information processing device.

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Miaoli County, Taiwan

Yu-Hui Lin