Yangtze Memory Technologies Co., Ltd.

Huazhong University of Science and Technology

Yu Huang

Jun Chen

Zhenyu Lu

Jifeng Zhu

Qian Tao

Xiaowang Dai

Li Hong Xiao

Si Ping Hu

Haohao Yang

Lan Yao

Kun Bao

A Man Zheng

Yushi Hu

Lidong Song

Yongna Li

Hai Jin

Xiaofei Liao

Long Zheng

A memory device includes an alternating layer stack including conductive/dielectric layer pairs stacked in a first direction, a first insulating layer on the alternating layer stack, a thickness of the first insulating layer being larger than a thickness of the dielectric layer, and a channel structure extending through the alternating layer stack and the first insulating layer along the first direction. The channel structure includes an epitaxial layer disposed at a first end of the channel structure away from the first insulating layer, a functional layer on the epitaxial layer and extending along the first direction, a channel layer covering a sidewall of the functional layer and in contact with the epitaxial layer, and a filling structure covering a sidewall of the channel layer. The memory device further includes a channel column structure at a second end of the channel structure near the first insulating layer and in contact with the channel layer, and a top selective gate structure over the first insulating layer and between neighboring channel column structures.

Three-dimensional memory devices and fabricating methods thereof

A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Staircase structure for memory device

A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.

The present invention relates to a graph-computing-oriented heterogeneous in-memory computing apparatus, comprising a memory control unit, a digital signal processing unit, and a plurality of analog signal processing units using the memory control unit.

Graph-computing-oriented heterogeneous in-memory computing apparatus and operational method thereof

Growing community of inventors

Hubei, China

Yu Huang