Mediatek Corporation

Yu-Hsuan Tu

Kang-Wei Hsueh

Chang-Shun Liu

Tse-Chi Lin

Che-Fu Liang

Yi-Fu Chen

Sy-Chyuan Hwu

An oscillator circuit is provided. The oscillator circuit includes a gated oscillator and a calibration circuit. The gated oscillator is arranged to generate an oscillator signal according to a control signal, and receive a gating signal to align an edge of the oscillator signal with an edge of the gating signal. The calibration circuit coupled to the gated oscillator is arranged to receive a first clock signal and a second clock signal, detect an alignment operation of the gated oscillator according to the first clock signal and a second clock signal and generate the control signal according to the detected alignment operation.

Methods for calibrating gated oscillator and oscillator circuit utilizing the same

A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer.

Delta-sigma analog-to-digital conversion apparatus and method thereof

An element-selecting method is utilized for selecting the converting elements of the DAC to perform the digital-to-analog conversion. The element-selecting method first determines whether the selected times of the converting elements are all equal or not. When the selected times of the converting elements are all equal, the element-selecting method determines a shifting-step according to the input signal and the number of the converting elements; otherwise, the element-selecting method determines the shifting-step to be a predetermined value. The element-selecting method then selects a converting element from the DAC by means of separating the converting element from a last selected converting element by the shifting-step. In this way, the error accumulated because of the mismatch of the converting elements is eliminated, and the toggle rate of the DAC is reduced. Hence, the glitch and the dynamic errors of the DAC are reduced, improving the performance of the DAC.

Element-selecting method capable of reducing toggle rate of digital to analog converter and module thereof

The invention provides a method of gain error calibration in a pipelined analog-to-digital converter (ADC). In one embodiment, a first stage and a second stage of the pipelined ADC share a common operational amplifier. The first stage is requested to generate the stage output signal thereof according to a first correction number. The second stage is also requested to generate the stage output signal thereof according to a second correction number. A plurality of stage output values generated by stages of the pipelined ADC are collected. The stage output values are respectively correlated with the first correction number and the second correction number to estimate a first gain error estimate of the first stage and a second gain error estimate of the second stage. The first gain error estimate and the second gain error estimate are weighted to obtain a predicted gain error for gain error calibration in the first stage and the second stage.

Method of gain error calibration in a pipelined analog-to-digital converter or a cyclic analog-to-digital converter

The invention provides an analog-to-digital converter (ADC). The ADC comprises a plurality of stages connected in series, a gain error correction module, and a look-ahead module. Each of the stages derives a stage output value from a stage input signal and generates a stage output signal as the stage input signal of a subsequent stage, wherein one of the stages is selected as a target stage for estimating a gain value thereof. The gain error correction module delivers a correction number to the target stage to affect the stage output signal of the target stage and the stage output values of subsequent stages of the target stage, receives at least one auxiliary output value from a look-ahead module dedicated to the target stage, and derives an error estimate of the gain value of the target stage from the stage output values and the auxiliary output value. The look-ahead module generates the auxiliary output value according to the stage output value of the target stage, wherein the auxiliary output value is not affected by the correction number.

Analog-to-digital converter and method of gain error calibration thereof

The invention provides a method for gain error estimation in an analog-to-digital converter. In one embodiment, the analog-to-digital converter comprises a plurality of stages. A series of correction numbers applied to a target stage selected from the stages are correlated with a series of calculation values calculated according to digital output values of the stages to generate a series of gain error estimates. The series of gain error estimates are multiplied by a series of updating parameters to obtain a series of first values. A series of previous gain error values are multiplied by one minus the corresponding updating parameters to obtain a series of second values, wherein the series of previous gain values are obtained by delaying the present gain error values. The series of first values and the series of second values are correspondingly added to obtain a series of present gain error values for gain error correction.

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Tainan, Taiwan

Yu-Hsuan Tu