Macronix International Co., Ltd.

Mediatek Corporation

Egis Technology Inc.

Igistec Co., Ltd.

Other

National Applied Research Laboratories

National Taiwan University

Medical and Pharmaceutical Industry Technology and Development Center

Hewlett-packard Development Company, L.p.

Industrial Technology Research Institute

Novatek Microelectronics Corp.

Inventec Corp.

Inventec (pudong) Technology Corporation

Merry Electronics (shenzhen) Co., Ltd.

Instrument Technology Research Center

Yu-Hsuan Lin

Po-Hao Tseng

Feng-Min Lee

Ming-Hsiu Lee

Chung-Yi Wang

Dai-Ying Lee

Yu-Yu Lin

Tang-Hung Po

Chih-Ching Chen

Yuh Cheng

Chao-Hung Wang

Ming-Yuan Cheng

Kuo-Jung Lan

Din-Ping Tsai

Erh-Kun Lai

Chao-I Wu

Kuo-Cheng Huang

Shu-Hung Chou

Gwo-Huei Wu

Hsun-Hao Chang

Hsin-Yi Tsai

Kai-Chieh Hsu

Ming-Jiou Yu

Jin-Bin Yang

Chia-Wei Liao

Min-Wei Hung

Tysh-Bin Liu

Ming-Liang Wei

You-Wen Chang

Tzu-Chieh Lin

Ching-Ning Chiu

Yuan-Ling Ku

Bruce C S Chou

Po-Kai Hsu

Wei-Chih Lin

Pi-Hai Liu

Tai-Shan Liao

Yu-Chee Tseng

Chih-Ching Yu

Chun-Yu Lin

Feng-Nien Ko

Shiue-Shin Liu

Chih-Chung Yang

Kuang-Hao Chiang

Hsien-Sheng Huang

Chiao-Wei Hsiao

Jyh-Shin Chen

Jong-Woei Chen

Shou-En Liu

Meng-Lung Chiang

Yueh-Feng Lee

Tian-Cih Bo

Tung-Yu Wu

Wen-Hong Wang

Wei-Yi Lin

Diego Jose Hernandez Garcia

Hsiang-Lan Lung

Yi-Chiuen Hu

Hua-Feng Chen

Santiago Reyero

Hsiao-yu Chou

Han-Chao Chang

Tzu-Yang Peng

Ying-Yu Kuo

Chih-Sheng Hung

Hui-Hsiung Lin

Wei-Lun Weng

Wei-Fu Wang

Lun-Wu Yeh

Yueh-Chu Chen

Hsien-Hsiang Chiu

Shih-Tsun Liang

Sung-Hua Chen

Chia-Lien Ma

Liang-Hua Chen

Chih-Ning Hsu

Joi-Tsang Shum

Tong-Long Fu

Shao-Chang Cheng

Yao-Li Huang

Zhe-Wei Kuo

Yu-Chang Lien

Cheng-Ru Li

Hsueh-Fang Yeh

Che-Yen Lu

Jui-Ching Chen

Che-Yi Lin

Chien-Chang Wu

Elissa Melor Berver

Cheng-Po Huang

Ming-Tsung Lin

A reservoir device, comprises a first transistor and a second transistor. A gate of the first transistor is coupled to a write word line, a drain of the first transistor is coupled to a write bit line. A source of the second transistor is coupled to a read source line, a drain of the second transistor is coupled to a read bit line, and a gate of the second transistor is coupled to a source of the first transistor. A storage node is located on a coupling point between the gate of the second transistor and the source of the first transistor. The reservoir device selectively performs a write operation, a read operation or a refresh operation in response to an input voltage received by the write word line, the write bit line, the read source line and the read bit line respectively.

Reservoir device and reservoir array

A three-dimensional (3D) memory device comprising word lines, bit lines, a 3D memory array, encoding circuits and sensing circuits is provided in the present disclosure. The 3D memory array comprises two-dimensional (2D) memory arrays and stores first to fourth neural network data related to at least one neural network model. Each of the 2D memory arrays is coupled to the word lines and the bit lines, and is configured to receive first and second input voltages and output corresponding first and second output currents. The encoding circuits are respectively coupled to the 2D memory arrays and configured to generate the first and second input voltages respectively based on the first and second neural network data. The sensing circuits are respectively coupled to the 2D memory arrays and configured to generate the third and fourth neural network data respectively based on the first and second output currents.

Three-dimensional memory device

A memory structure includes insulating layers, gate layers, a first doping layer, channel layers, a columnar channel, second doping layers, a first dielectric layer, second dielectric layers, a third dielectric layer, and fourth dielectric layers. The first doping layer and the columnar channel penetrate through the insulating layers and the gate layers that are alternately stacked. The channel layers are connected to the first doping layer, in which the channel layers and the insulating layers are alternately stacked. The second doping layers surround the columnar channel and are connected to the channel layers. The first dielectric layer is between the first doping layer and the gate layers. The second dielectric layers are between the second doping layers and the gate layers. The third dielectric layer is between the columnar channel and the second doping layers. The fourth dielectric layers are between the channel layers and the gate layers.

Memory structure, manufacturing method thereof, and operating method thereof

An in-memory computation device and computation method are provided. The in-memory computation method includes: providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values; respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer; providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.

In-memory computation device and in-memory computation method to perform multiplication operation in memory cell array according to bit orders

A hyperdimensional computing device includes a non-volatile memory cell array and a first operation circuit. The non-volatile memory cell array is coupled to a plurality of first word lines. The non-volatile memory cell array has a plurality of memory cell groups, a plurality of first memory cells of each of the memory cell groups are coupled to a same first word line of the first word lines, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit receives at least one of the data vectors through bit lines and generates a bundled data vector according to the at least one of the data vectors.

Hyperdimensional computing device

A storage device for generating an identity code, includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores several first data having several bits. The second storage circuit stores several second data having several bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, and simultaneously reads the first data from the first storage circuit to form a second sequence. The reading circuit includes a processing circuit which simultaneously receives the first sequence and the second sequence, selects a first portion of the second sequence to form a target sequence according to the first sequence, and outputs the target sequence to serve as an identity code. Logical values of the bits of the first data and the second data are randomly distributed or pre-defined by a user.

Storage device for generating identity code and identity code generating method

An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.

Artificial neural network operation circuit and in-memory computation device thereof

The present invention discloses a memory and a training method for neural network based on memory. The training method includes: obtaining one or more transfer functions of a memory corresponding to one or more influence factors; determining a training plan according to an ideal case and the one or more influence factors; training the neural network according to the training plan and the one or more transfer functions to obtain a plurality of weights of the trained neural network; and programming the memory according to the weights.

Memory and training method for neural network based on memory

A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.

Hybrid IMS CAM cell, memory device and data search method

An in-dynamic memory search device and an operation method thereof are provided. The in-dynamic memory search device includes at least one word line, at least two bit lines, at least one match line, at least one unit cell, at least two search lines, at least one pre-charge unit and at least one sense unit. The unit cell includes two storage elements and two search transistors. Each of the storage elements includes a write transistor and a read transistor. The write transistor is connected to the word line and one of the bit lines. The read transistor is connected to the write transistor and the match line. The search transistors are respectively connected to the read transistors. The search lines are respectively connected to the search transistors. The pre-charge unit is connected to the match line. The sense unit is connected to the match line.

In-dynamic memory search device and operation method thereof

A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

Method for manufacturing memory device

The application provides a content addressable memory (CAM) memory device, a CAM cell and a method for searching and comparing data thereof. The CAM device includes: a plurality of CAM cells; and an electrical characteristic detection circuit coupled to the CAM cells; wherein in data searching, a search data is compared with a storage data stored in the CAM cells, the CAM cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.

Content addressable memory device, content addressable memory cell and method for single-bit multi-level data searching and comparing

The application discloses an integrated memory device, a manufacturing method and an operation method thereof. The integrated memory cell includes: a first memory cell; and an embedded second memory cell, serially coupled to the first memory cell, wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell.

Memory cell, memory device manufacturing method and memory device operation method thereof

A storage device for generating an identity code and an identity code generating method are disclosed. The storage device includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores a plurality of first data and the first data have a plurality of bits. The second storage circuit stores a plurality of second data and the second data have a plurality of bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, selects a first portion of the first data according to the first sequence, reads the first portion of the first data from the first storage circuit to form a target sequence and outputs the target sequence to serve as an identity code.

An analog content-address memory (analog CAM) having approximation matching and an operation method thereof are provided. The analog CAM includes an inputting circuit, at least one analog CAM cell and an outputting circuit. The inputting circuit is configured to provide an inputting data. The analog CAM cell is connected to the inputting circuit and receives the inputting data. The analog CAM cell has a mild swing match curve whose highest point corresponds to a stored data. A segment from the highest point of the mild swing match curve to a lowest point of the mild swing match curve corresponds to at least three data values. The outputting circuit is connected to the analog CAM cell and receives a match signal from the analog CAM cell. The outputting circuit outputs a match approximation level according to the match signal.

Analog content-address memory having approximation matching and operation method thereof

Growing community of inventors

Taichung, Taiwan

Yu-Hsuan Lin