Silicon Motion, Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Elite Semiconductor Memory Technology, Inc

Yu-Hsuan Cheng

Hsin-Chi Chen

Yung-Lung Hsu

Chia-Yu Wei

Chin-Hsun Hsiao

Jian-Sing Liou

Po-Chun Chiu

Ching-Ling Cheng

A data storage apparatus and a method for preventing data error using the same are provided. The data storage apparatus includes a memory and a memory controller. The memory includes a plurality of blocks. The memory controller is coupled to the memory and configured to perform the following operations: recording a read count of a target block of the memory; performing an error bit check on a free storage space of the target block when the read count of the target block meets a condition; and programming a dummy data to the free storage space of the target block in response to the determination that the check result is negative.

Data storage apparatus and method for preventing data error using the same

A method for determining a resistance calibration direction in ZQ calibration of a memory device includes: repeatedly comparing a reference voltage with an target voltage by a comparator to obtain an odd plurality of comparison outputs, each of the comparison outputs being one of a high-level state and a low-level state; determining a majority of the comparison outputs for their states by a ZQ calibration controller; and determining a resistance calibration direction according to the majority by the ZQ calibration controller so that the ZQ calibration controller generates a calibration code based on the resistance calibration direction and applies the calibration code to a resistance calibration unit to adjust the target voltage via the resistance calibration unit.

Method for determining resistance calibration direction in ZQ calibration of memory device

An image sensor including a substrate, a trench isolation, a plurality of image sensing units, at least one phase detection unit, and an interconnection layer is provided. The trench isolation is in the substrate, and a plurality of active areas of the substrate are separated from each other by the trench isolation. The image sensing units and the at least one phase detection unit are in the active areas arranged in an array, and a sensing area of the at least one phase detection unit is smaller than a sensing area of each of the image sensing units. The interconnection layer is disposed on the image sensing units and the at least one phase detection unit. In addition, a method of fabricating an image sensor is also provided.

Image sensor and method for manufacturing the same

An example of the invention provides a digital delay unit that is made up of a plurality of NAND gates. The digital delay unit includes a first delay path and a second delay path. The first delay path is coupled between a first input terminal and an output terminal to provide a basic time delay which is caused by one NAND gate. The second delay path is coupled between a second input terminal and the output terminal to provide at least three basic time delays.

Digital delay unit and signal delay circuit

A phase detector, arranged for comparing a phase of a first clock with a phase of a second clock. The phase detector includes a phase detection stage and a metastable prevention stage. The phase detection stage is arranged to receive the first clock and the second clock, and to output a phase comparison result in accordance with the phase of the first clock and the phase of the second clock. The metastable prevention stage is arranged to receive the phase comparison result, and to output a stable phase comparison result in accordance with the phase comparison result.

Growing community of inventors

Taipei, Taiwan

Yu-Hsuan Cheng