Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Hsiung Wang

Chen-Chin Liu

Han-Yu Chen

Wan-Chen Chen

Wei Cheng Wu

Yi Hsien Lu

Juo-Li Yang

Harry-Hak-Lay Chuang

Wen-Ting Chu

Eric Chen

Hsien-Wei Chin

Chih-Ren Hsieh

Tung-Sheng Hsiao

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Semiconductor device and manufacturing method thereof

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.

Inter-digitated capacitor in flash technology

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes disposed over a substrate and a lower electrode disposed between the plurality of upper electrodes. A charge storage layer continuously extends from along a first side of the lower electrode to along a second side of the lower electrode opposing the first side. The charge storage layer separates the lower electrode from the plurality of upper electrodes and the substrate. A silicide is disposed over the lower electrode and the plurality of upper electrodes. The silicide has sidewalls that are laterally separated by a distance directly overlying a top of the charge storage layer.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes separated from a semiconductor substrate by a first dielectric layer. A lower electrode is laterally disposed between the plurality of upper electrodes and between sidewalls of the semiconductor substrate. A second dielectric layer lines opposing sidewalls and a lower surface of the lower electrode. The second dielectric layer laterally separates the lower electrode from the plurality of upper electrodes and from the sidewalls of the semiconductor substrate.

Inter-digitated capacitor in split-gate flash technology

The present disclosure relates to an integrated chip having an inter-digitated capacitor, and an associated method of formation. In some embodiments, the integrated chip has a plurality of upper electrodes separated from a substrate by a first dielectric layer. A plurality of lower electrodes vertically extend from between the plurality of upper electrodes to locations embedded within the substrate. A charge trapping dielectric layer is arranged between the substrate and the plurality of lower electrodes and between the plurality of upper electrodes and the plurality of lower electrodes. The charge trapping dielectric layer has a plurality of discrete segments respectively lining opposing sidewalls and a lower surface of one of the plurality of lower electrodes.

The present disclosure relates to an inter-digitated capacitor that can be formed along with split-gate flash memory cells and that provides for a high capacitance per unit area, and a method of formation. In some embodiments, the inter-digitated capacitor has a well region disposed within an upper surface of a semiconductor substrate. A plurality of trenches vertically extend from the upper surface of the semiconductor substrate to positions within the well region. Lower electrodes are arranged within the plurality of trenches. The lower electrodes are separated from the well region by a charge trapping dielectric layer arranged along inner-surfaces of the plurality of trenches. A plurality of upper electrodes are arranged over the semiconductor substrate at locations laterally separated from the lower electrodes by the charge trapping dielectric layer and vertically separated from the well region by a first dielectric layer.

Interdigitated capacitor in split-gate flash technology

A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region.

Method for manufacturing a finger trench capacitor with a split-gate flash memory cell

Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate including a flash memory region and a capacitor region. A flash memory cell is arranged over the flash memory region and includes a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell. The flash memory cell also includes a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer. A capacitor is arranged over the capacitor region and includes: a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and separated from one another by a capacitor dielectric layer. The capacitor dielectric layer and control gate dielectric layer are made of the same material.

Interdigitated capacitor to integrate with flash memory

Some embodiments of the present disclosure relate to an integrated circuit (IC) arranged on a semiconductor substrate, which includes a flash region, a capacitor region, and a logic region. An upper substrate surface of the capacitor region is recessed relative to respective upper substrate surfaces of the flash and logic regions, respectively. A capacitor, which includes a polysilicon bottom electrode, a conductive top electrode arranged over the polysilicon bottom electrode, and a capacitor dielectric separating the bottom and top electrodes; is disposed over the recessed upper substrate surface of the capacitor region. A flash memory cell is disposed over the upper substrate surface of the flash region. The flash memory cell includes a select gate having a planarized upper surface that is co-planar with a planarized upper surface of the top electrode of the capacitor.

Integration techniques for MIM or MIP capacitors with flash memory and/or high-&#x3ba; metal gate CMOS technology

A semiconductor device includes a substrate; a storage element disposed over the substrate in a first region; a control gate disposed over the storage element; a high-k dielectric layer disposed on the substrate in a second region adjacent the first region; and a metal select gate disposed over the high-k dielectric layer and adjacent to the storage element and the control gate.

Split-gate device and method of fabricating the same

A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process.

Growing community of inventors

Zhubei, Taiwan

Yu-Hsiung Wang