Ememory Technology Inc.

Yu-Hsiung Tsai

Wein-Town Sun

Yuan-Tai Lin

Shang-Wei Fang

Po-Hao Huang

Chun-Yuan Lo

Ching-Yuan Lin

Chi-Yi Shao

Chiun-Chi Shen

Chao-Wei Kuo

Po-Hao Lee

Chia-Jung Hsu

Chia-Fu Chang

Yin-Chang Chen

Wei-Wu Liao

Ying-Je Chen

Jie-Hau Huang

Che-Wei Chang

Hong-Yi Liao

Cheng-Jye Liu

Chi-Chang Lin

Chih-Bin Kuo

The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.

Non-volatile memory apparatus and erasing method thereof

A nonvolatile memory includes a memory array. The memory array is connected to m word lines and (2+n) bit line pairs. These bit line pairs include an erase bit line pair, a program bit line pair and n data bit line pairs. Each word line is connected with (2+n) differential cells of a corresponding row. The (2+n) differential cells include an erase flag differential cell, a program flag differential cell and n data differential cells. The erase flag differential cell is connected with the erase bit line pair. The program flag differential cell is connected with the program line pair. The n data differential cells are connected with the data line pairs. The n data differential cells are determined as erased cells or programmed cells according to setting conditions of the erase flag differential cell and the program flag differential cell.

Nonvolatile memory having memory array with differential cells

A bias voltage generator for providing a control voltage and a source line voltage to a memory array includes a reference voltage generating circuit and a voltage converting circuit. The reference voltage generating circuit receives a program signal or an erase signal, and generates a reference voltage. If the program signal is received by the reference voltage generating circuit, the reference voltage has a positive temperature coefficient. If the erase signal is received by the reference voltage generating circuit, the reference voltage has a negative temperature coefficient. The voltage converting circuit converts the reference voltage into the control voltage and the source line voltage. The voltage converting circuit enlarges the reference voltage by a first magnification so as to produce the source line voltage, and enlarges the reference voltage by a second magnification so as to produce the control voltage.

Bias generator for flash memory and control method thereof

A sensing method of a current sensing amplifier is provided used for determining a storing state of a cell of a non-volatile memory device during a read cycle. After a sensing node and a reference node are adjusted to a constant voltage, the sensing node and the reference node are maintained in a floating state. Then, the sensing node is connected with a data line to receive a cell current from the cell, and the reference node is connected with a reference current source to receive a reference current from the reference current source. When a reference voltage of the reference node reaches a preset voltage, the storing state of the cell is determined according to a relationship between a sensing voltage of the sensing node and the preset voltage.

Current sensing amplifier and sensing method thereof

The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.

Flash memory

A clock trimming apparatus includes an oscillator, a judging unit, a latching unit, and a tracking unit. The oscillator has an input terminal receiving a bias signal and an output terminal generating a clock signal. After a frequency division is performed on the clock signal, the judging unit generates a frequency-divided signal. If the frequency-divided signal matches the reference signal, a pass signal generated by the judging unit is activated. The latching unit is used for generating a trimming completion signal. After the pass signal is activated, the trimming completion signal is activated. The tracking unit is used for counting a pulse number of the reference signal and providing the bias signal to the oscillator according to a trimming code. After the trimming completion signal is activated, the trimming code is stopped being adjusted.

Clock trimming apparatus and associated clock trimming method

A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage.

Flash memory and associated programming method

The invention provides a flash memory apparatus including at least one flash memory array block and a sense amplifying module. The flash memory array block comprises N storage columns, N reference word-line cell units and a reference storage column, wherein N is a positive integer. Each of the reference word-line cell units disposed in each of the storage columns, wherein, the reference word-line cell units further coupled to a reference word line and a dummy word line. The reference storage column includes a plurality of reference bit-line cells, the reference word line and the dummy word line, one of the reference bit-line cells which coupled to the reference word line is coupled to a reference bit line. The sense amplifying module compares currents from one of the bit lines and the corresponding reference bit line to generate at least one sensing result.

Flash memory apparatus with reference word lines

The present invention provides a memory architecture and associated serial direct access (SDA) circuit. The memory architecture includes a memory of a parallel interface and a serial direct access (SDA) circuit. The SDA circuit includes an enable pin, a serial pin and an auto-test module. The enable pin receives an enable bit, wherein the SDA circuit is selectively enabled and disabled in response to the enable bit. When the SDA circuit is enabled, the serial pin sequentially relaying a plurality of serial bits, such that each of the serial bits is associated with one of parallel pins of the parallel interface; in addition, the auto-test module can perform a built-in test of the memory associated with the serial bits.

Memory architecture and associated serial direct access circuit

A word line boost circuit including a first address transfer detector, a second address transfer detector and a boost operation unit is provided. The first address transfer detector generates a first detection pulse in response to variation of a row address signal. The second address transfer detector generates a second detection pulse in response to variation of a column address signal. Moreover, the boost operation unit generates a selection voltage by using a boost voltage according to the first detection pulse, and determines whether or not to use the boost voltage to generate the selection voltage according to a delay time between the first detection pulse and the second detection pulse.

Word line boost circuit

A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.

Non-volatile memory device with program current clamp and related method

A flash memory device with auto-trimming functionality includes a memory cell array comprising first memory cells and a fuse sector, a read circuit for reading a memory state of the first memory cells, an offset circuit for outputting offset current values, and an auto-trimming circuit. The auto-trimming circuit has a register for storing a current characteristic, a current control module for modifying input current applied to a first memory cell under test at a first address according to the memory state, and updating the current characteristic to the modified input current, an address counter for starting application of the modified input current to a second memory cell at a second address for test when reading the first memory cell passes, and a programming circuit for programming the fuse sector according to the current characteristic and the offset current values.

Method of setting trim codes for a flash memory and related device

A control driver for non-volatile memory includes a driving circuit, a level shift up circuit, and a select circuit. The select circuit receives a plurality of decoding signals, asserts a select signal when all of the decoding signals are asserted, and does not assert the select signal when any of the decoding signals is not asserted. The level shift up circuit receives the select signal, outputs the pull-up signal at a first voltage when the select signal is asserted, and outputs the pull-up signal at a second voltage when the select signal is not asserted. The driving circuit has a pull-up transistor for pulling up a control line signal according to the pull-up signal, and a pull-down transistor for pulling down the control line signal according to the pull-up signal.

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Hsinchu, Taiwan

Yu-Hsiung Tsai