Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Hsing Chang

Shih-Chang Liu

Ming Chyi Liu

Chia-Shiung Tsai

Chang-Ming Wu

Sheng-Chieh Chen

Yuan-Tai Tseng

Ru-Liang Lee

Ming-Chyi Liu

Harry-Hak-Lay Chuang

Wei Cheng Wu

Chern-Yow Hsu

Yao-Wen Chang

Ping-Yin Liu

Hsun-Chung Kuang

Xin-Hua Huang

Yeong-Jyh Lin

Chia-Hua Lin

Wei-Hang Huang

Yi-Min Chen

Te-Hsien Hsieh

Chern-yow Hsu

Wen-Ting Chu

Wei-Cheng Wu

Yu-Wen Liao

Yung-Chang Chang

Fu-Ting Sung

Ching-Pei Hsieh

Pei-Lun Wang

In some embodiments, the present disclosure relates to a display device that includes a reflector electrode coupled to an interconnect structure. An isolation structure is disposed over the reflector electrode, and a transparent electrode is disposed over the isolation structure. Further, an optical emitter structure is disposed over the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and comprises an outer portion that directly overlies the top surface of the isolation structure. A hard mask layer is arranged directly between the top surface of the isolation structure and the outer portion of the via structure.

Hard mask layer below via structure in display device

In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

Via landing on first and second barrier layers to reduce cleaning time of conductive structure

A semiconductor device includes: a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate; a first insulating plate disposed over the first conductive plate and the second conductive plate; a third conductive plate disposed over the first insulating plate; a second insulating plate disposed over the third conductive plate; a fourth conductive plate disposed on one side of the second conductive plate opposite to the first conductive plate; a first conductive spacer disposed on the first insulating plate adjacent to the fourth conductive plate; a first conductive via penetrating the second insulating plate, the first insulating plate, and the first conductive plate, wherein the first conductive via is electrically coupled to the first conductive plate; and a second conductive via penetrating the fourth conductive plate, wherein the second conductive via is electrically coupled to the fourth conductive plate.

Semiconductor device and method of forming the same

Some embodiments pertain to a semiconductor device. The semiconductor device includes a semiconductor substrate including a trench extending downward into an upper surface of the semiconductor substrate. The trench includes a bottom surface and a plurality of scallops along sidewalls of the trench. An oxide layer lines the bottom surface and the sidewalls of the trench. The oxide layer has varying thicknesses along the sidewalls of the trench at different depths. The varying thicknesses step down at discrete increments as a depth into the trench increases.

High aspect ratio bosch deep etch

The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.

Deposition system for high accuracy patterning

A semiconductor device includes: a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate; a first insulating plate disposed over the first conductive plate and the second conductive plate; a third conductive plate disposed over the first insulating plate; a second insulating plate disposed over the third conductive plate; a fourth conductive plate disposed over the second insulating plate; a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate, wherein the first conductive via is electrically coupled to the fourth conductive plate and the first conductive plate; and a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate, wherein the second conductive via is electrically coupled to the third conductive plate and the second conductive plate.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a display pixel in which a bottom electrode and a reflector are separate and border. A light emission device overlies the reflector, and a top electrode overlies the light emission device. A coupling structure extends from the bottom electrode, alongside the reflector, to an interface between the light emission device and the reflector to electrically couple the bottom electrode to the light emission device.

Pixel structure for displays

A deep trench is formed in a substrate, and a layer stack including at least three metallic electrode plates interlaced with at least two node dielectric layers is formed in, and over, the deep trench. A contact-level dielectric material layer over the layer stack, and contact via cavities are formed therethrough. The depths of the contact via cavities are differentiated by selectively increasing the depth of a respective subset of the contact via cavities by performing at least twice a combination of processing steps that includes an etch mask formation process and an etch process. A combination of a dielectric contact via liner and a plate contact via structure can be formed within each of the contact via cavities. Plate contact via structures that extend through any metallic electrode plate can be electrically isolated from such a metallic electrode plate by a respective dielectric contact via liner.

Deep trench capacitor including self-aligned plate contact via structures and methods of forming the same

A method of forming a semiconductor device includes: depositing a first conductive plate and a second conductive plate adjacent to the first conductive plate; depositing a first insulating plate on the first conductive plate and the second conductive plate; depositing a third conductive plate on the first insulating plate; depositing a second insulating plate on the third conductive plate; forming a fourth conductive plate on the second insulating plate; forming a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate; and forming a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate.

In some methods, a first recess is etched in a selected region of a substrate. A first polymer liner is formed on sidewalls and a bottom surface of the first recess. A portion of the first polymer liner is removed from the bottom surface, and a remaining portion of the first polymer liner is left along the sidewalls. The first recess is deepened to establish a second recess while the remaining portion of the first polymer liner is left along the sidewalls. A first oxide liner is formed along the sidewalls and along sidewalls and a bottom surface of the second recess. A portion of the first oxide liner is removed from a bottom surface of the second recess, while a remaining portion of the first oxide liner is left on the sidewalls of the first recess and the sidewalls of the second recess.

High aspect ratio Bosch deep etch

Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Cell boundary structure for embedded memory

A semiconductor device includes a capacitive device, a first conductive via, and a second conductive via. The capacitive device includes a first conductive plate, a first insulating plate, a second conductive plate, a second insulating plate, and a third conductive plate. The first conductive via is electrically coupled to the first conductive plate and the third conductive plate, and the first conductive via penetrated through a first film stack with a first thickness. The second conductive via is electrically coupled to the second conductive plate, and the second conductive via penetrated through a second film stack with a second thickness. The second thickness is substantially equal to the first thickness.

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Taipei, Taiwan

Yu-Hsing Chang