Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Hsien Chu

Chiang-Ming Chuang

Cheng-Huan Chung

Cheng-Ming Wu

Yu-Chang Jong

Wen-Chih Chiang

Chih-Ming Lee

Ling Mei Lin

A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.

Method of forming high voltage transistor and structure resulting therefrom

The present disclosure relates to a flash memory cell that includes a substrate and a floating gate structure over the substrate. The floating gate structure includes a first portion having a first top surface and a first thickness. The floating gate structure also includes a second portion having a second top surface and a second thickness that is different from the first thickness. The floating gate structure further includes a sidewall surface connecting the first and second top surfaces, and an angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle. The flash memory cell also includes a control gate structure over the first and second portions of the floating gate structure.

Flash memory cell structure with step-shaped floating gate

Growing community of inventors

Kaohsiung, Taiwan

Yu-Hsien Chu