Phison Electronics Corporation

Yu-Hsiang Lin

Shao-Wei Yen

Kuo-Hsin Lai

Wei Hung Lin

Cheng-Che Yang

Kuo-Yi Cheng

Bo Lun Huang

Yu-Cheng Hsu

Tien-Ching Wang

Chih-Kang Yeh

Shih-Jia Zeng

Yu-Siang Yang

Li-Chun Liang

Siu-Tung Lam

Pochiao Chou

A decoding method, comprising: sending a first read command sequence corresponding to a host system to read a first physical unit of a physical unit group to obtain a first data frame; responding to a decoding failure of a first single-frame decoding performed on the first data frame, sending a plurality of second read command sequences to read a plurality of second physical units in the physical unit group to obtain a plurality of second data frames; respectively performing a second single-frame decoding on the second data frames; performing a XOR operation on the corresponding data frame of each physical unit of the physical unit group to obtain first error evaluation information; generating enhanced first error evaluation information based on the first error evaluation information; and performing a third single-frame decoding on the first data frame based on the enhanced first error evaluation information.

Decoding method, memory storage device and memory control circuit unit

A decoding parameter updating method, a memory storage device, and a memory control circuit unit are disclosed. The method includes the following. A reading command sequence is sent to a rewritable non-volatile memory module to instruct reading of first data from a first physical unit based on multiple read voltage levels. A logical operation is performed on a first data group to obtain decoding index information corresponding to the first data group. The first data group includes the first data and second data read from a second physical unit. Error evaluation information corresponding to a first voltage interval among multiple voltage intervals is obtained according to the first data and the decoding index information. A first decoding parameter corresponding to the first voltage interval is updated according to the error evaluation information.

Decoding parameter updating method, memory storage device and memory control circuit unit

A decoding parameter updating method, a memory storage device, and a memory control circuit unit are provided. The method includes: sending a read command sequence to a rewritable non-volatile memory module to instruct to read first data from a first physical unit based on multiple read voltage levels; decoding the first data according to multiple decoding parameters to obtain second data, wherein the decoding parameters respectively correspond to multiple voltage intervals, and the voltage intervals are defined by the read voltage levels; obtaining first error evaluation information corresponding to a first voltage interval among the voltage intervals according to the first data and the second data; and updating a first decoding parameter corresponding to the first voltage interval according to the first error evaluation information.

Decoding parameter updating method, memory storage device, and memory control circuit unit

A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending a plurality of read command sequences configured to instruct a rewritable non-volatile memory module to read a first physical unit by using a plurality of read voltage levels; after the read command sequences are sent, receiving first data from the rewritable non-volatile memory module, where the first data includes replacement data corresponding to a plurality of first bits reflecting a read result of a first memory cell by using the read voltage levels, and a data amount of the first data is less than a total data amount of the first bits; after the first data is received, performing data restoration on the first data to obtain a plurality of second bits; performing a decoding operation according to the second bits.

Decoding method based on replacement data with reduced data amount, memory storage device and memory control circuit unit

An encoding control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing, by an encoding circuit, a first encoding operation to generate first parity data according to write data, a first sub-matrix and a second sub-matrix of a parity check matrix; performing, by the encoding circuit, a second encoding operation to generate second parity data according to the write data, the first parity data, a third sub-matrix, a fourth sub-matrix and a fifth sub-matrix of the parity check matrix; and sending a first write command sequence to instruct a storing of the write data, the first parity data and the second parity data to a rewritable non-volatile memory module.

Encoding control method, memory storage device and memory control circuit unit

A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: respectively performing a single-frame decoding on a plurality of first data frames read from a physical unit set, the physical unit set contains a plurality of first physical units in a rewritable non-volatile memory module; in response to an entire decoding result of the first data frames meeting a first condition, obtaining error evaluation information related to the physical unit set, and the error evaluation information reflects a bit error status of the physical unit set; obtaining reliability information according to the error evaluation information; and performing the single-frame decoding on a second data frame read from one of the first physical units according to the reliability information.

Decoding method, memory storage device, and memory control circuit unit

A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data; executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data; reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data; and executing a global decoding operation on the second data according to the global parity data.

Memory control method, memory storage device, and memory control circuit unit

A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.

Data writing method, memory controlling circuit unit and memory storage device

A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a read command sequence for reading a plurality of bits from the memory cells; calculating a first count value of a first value and a second count value of a second value in the bits; and adjusting a decoding parameter corresponding to the bits to a specific decoding parameter according to the first count value and the second count value, and performing a decoding operation according to the specific decoding parameter, where the adjusted decoding parameter affects a probability that the bits are considered as an error bit in the decoding operation.

Decoding method, memory storage device, and memory controlling circuit unit

A decoding method, a memory control circuit unit, and a memory storage device are provided. The method includes: configuring a plurality of read voltage categories, wherein the read voltage categories respectively have a plurality of representative read voltage sets; reading a first physical programming unit according to the representative read voltage sets and executing a decoding operation to obtain a plurality of decoded information; choosing a first read voltage category according to the plurality of decoded information; and reading the first physical programming unit according to the first read voltage sets in the first read voltage category and executing the decoding operation.

Decoding method, memory control circuit unit and memory storage device

A decoding method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the invention. The method includes: reading at least one memory cells by using at least one read voltage level to obtain a codeword; performing a parity check operation on the codeword by an error checking and correcting circuit to generate a syndrome sum corresponding to the codeword; and dynamically adjusting a first parameter used by the error checking and correcting circuit in a first decoding operation based on whether the syndrome sum is less than a first threshold value and performing the first decoding operation on the codeword by the error checking and correcting circuit by using the first parameter.

A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Ybit in the X bits of the first codeword is different from a Ybit in the X bits of the second codeword, recording the Ybit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.

Bit tagging method, memory control circuit unit and memory storage device

A decoding method is provided according to an exemplary embodiment of the invention. The decoding method includes: reading a data set from at least two physical units of a rewritable non-volatile memory module by using at least one read voltage level; performing a first-type decoding operation for first data by using the data set and recording decoding information of the first-type decoding operation if the data set conforms to a default condition; adjusting reliability information corresponding to the first data according to the recorded decoding information, and the reliability information is not used in the first-type decoding operation, and the adjusted reliability information is different from default reliability information corresponding to the first data; and performing a second-type decoding operation for the first data according to the adjusted reliability information.

In one exemplary embodiment, the decoding method includes: reading first data from a plurality of first memory cells of a rewritable non-volatile memory module; performing a first decoding operation on the first data based on a first decoding condition; and performing a second decoding operation on the first data based on a second decoding condition if the first decoding operation conforms to a first default status, where a strict level of locating an error bit in the first data based on the second decoding condition is higher than a strict level of locating the error bit in the first data based on the first decoding condition. Therefore, a decoding efficiency of a memory storage device can be improved.

A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved.

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Yunlin County, Taiwan

Yu-Hsiang Lin