United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Untied Microelectronics Corp.

Yu-Hsiang Hung

Ssu-I Fu

Jyh-Shyang Jenq

Chih-Kai Hsu

Chung-Fu Chang

Yen-Liang Wu

Wei-Chi Cheng

Chao-Hung Lin

Chia-Jong Liu

Shih-Hung Tsai

Chien-Ting Lin

Li-Wei Feng

Yi-Wei Chen

Man-Ling Lu

Wen-Jiun Shen

Cheng-Guo Chen

Yu-Hsiang Lin

Pei-Yu Chou

Ming-Te Wei

Po-Chao Tsao

Shin-Chuan Huang

Ming-Hua Tsai

Home-Been Cheng

Jung Han

Chih-Mou Lin

Ming-Chi Li

Tzu-Lang Shih

Shih-Fang Tzou

Ying-Chiao Wang

Chia-Jui Liang

Ching-Yu Chang

Chia-Wen Liang

Ming-Tsung Chen

Tsung-Mu Yang

Ying-Tsung Chen

Cho-Han Fan

Yu-Cheng Tung

En-Chiuan Liou

Feng-Yi Chang

Fu-Che Lee

Chun-Hsien Huang

Chin-Hung Chen

Yu-Tse Kuo

An-Chi Liu

Shu-Ru Wang

Chun-Ya Chiu

Wei-Lun Hsu

Shih-Fang Hong

Ying-Chih Lin

I-Chang Wang

Gang-Yi Lin

Chi-Ting Wu

Hon-Huei Liu

Chia-Hsun Tseng

Hsiang-Ying Wang

Guang-Yaw Hwang

Chia-Liang Liao

Jun-Jie Wang

Chih-Wei Wu

Mei-Chen Chen

A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

Manufacturing method of semiconductor device including gate oxide layer

A semiconductor device includes a gate structure on a substrate, a spacer around the gate structure, and a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

Semiconductor device and method for fabricating the same

Semiconductor device including gate oxide layer

Semiconductor device including gate oxide layer and manufacturing method thereof

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width Xand a width X. The width Xis aligned with the top portion of the rounding hard mask in a horizontal direction, and the width Xis aligned with the bottom portion of the rounding hard mask in the horizontal direction, Xis greater than or equal to X

Semiconductor device and manufacturing method thereof

The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width X1 and a width X2. The width X1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, X1 is greater than or equal to X2.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.

A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

Method of forming fin-shaped structure

A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.

Method of forming layout definition of semiconductor device

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.

Method for fabricating cap layer on an epitaxial layer

A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a spacer adjacent to the gate structure; forming a recess adjacent to the spacer; forming a buffer layer in the recess, wherein the buffer layer comprises a crescent moon shape; and forming an epitaxial layer on the buffer layer.

Method for fabricating semiconductor device

Growing community of inventors

Tainan, Taiwan

Yu-Hsiang Hung