United Microelectronics Corp.

Yu-Ho Chiang

Hua-Chou Tseng

Chun-Yao Ko

Cheng-Wen Fan

Chien-Kuo Yang

Chih-Yuh Tzeng

Victor Chiang Liang

Wai-Yi Lien

Victor-Chiang Liang

Chih-Chun Wang

Hsin-Hsing Chen

Tsung-Yen Pan

A dummy cell pattern includes a dummy diffusion pattern disposed within a predetermined region A; a trench isolation pattern encompassing the dummy diffusion pattern in the predetermined region A; a first dummy gate pattern disposed on the dummy diffusion pattern with two ends of the first dummy gate pattern extending above the trench isolation pattern, thereby forming overlapping areas Cand C; and a second dummy gate pattern directly on the trench isolation pattern forming an overlapping area C therebetween, wherein the combination of C, Cand C is about 5%-20% of the predetermined region A.

Dummy cell pattern for improving device thermal uniformity

A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

Method for reducing capacitance variation between capacitors

Structure of capacitor set

A capacitance dielectric layer is provided. The capacitance dielectric layer includes a first dielectric layer, a second dielectric layer and a silicon nitride stacked layer. The silicon nitride stacked layer is disposed between the first dielectric layer and the second dielectric layer. The structure of the capacitance dielectric layer permits an increase in the capacitance per unit area by decreasing the thickness of the capacitance dielectric layer and eliminates the problems of having a raised leakage current and a diminished breakdown voltage.

Capacitance dielectric layer and capacitor

A metal-insulator-metal capacitor structure includes a lower electrode, a buffer layer, a barrier layer, a dielectric layer and an upper electrode. The lower electrode is disposed in the buffer layer. The barrier layer covers part of the lower electrode and is disposed between the lower electrode and the upper electrode. The buffer layer serves as an etching stop layer to define the dielectric layer. The dielectric layer in the metal-insulator-metal capacitor structure has a uniform and ideal thickness.

Metal-insulator-metal capacitor structure

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Taichung, Taiwan

Yu-Ho Chiang