Toshiba Memory Corporation

Kioxia Corporation

Yu Hirotsu

Naoki Yamamoto

Osamu Matsuura

Ryota Katsumata

Masayoshi Tagami

Hiroshi Nakaki

Hisashi Kato

Kazuhiro Nojima

Toru Matsuda

Jun Nishimura

Takamasa Ito

Shoichi Miyazaki

Ken Komiya

Keisuke Suda

Taichi Iwasaki

Yoshinori Nakakubo

Hisashi Harada

Ayaha Hachisuga

Sota Matsumoto

Akira Yotsumoto

Kazuhiro Tomishige

Yukie Miyazaki

Ayumi Watarai

Kanako Shiga

Mitsunori Masaki

Semiconductor memory device includes: a first and second member each extending in a first direction in a boundary part between a first and second block region and arranged in the first direction; a support pillar arranged between the first and second member at the boundary part; conductive layers separated from one another and arranged in a third direction and split by the first and second member, and the support pillar into a first and second portion; and a memory pillar penetrating through the conductive layers. The support pillar includes a lower and upper pillar. A side face of the lower pillar and an extension of a side face of the upper pillar are displaced from each other in a plane based on a second and the third direction.

Semiconductor memory device

A semiconductor memory according to an embodiment includes first and second areas, an active region, a non-active region, a first stacked body, a plurality of first pillars, a first contact, a second stacked body, and a second contact. The active region includes part of each of the first and second areas. The non-active region includes part of each of the first and second areas. The second stacked body is in the non-active region. The second stacked body includes second insulators and second conductors which are alternately stacked. A second contact is in contact with a second conductor in a first interconnect layer and a second conductor in a second interconnect layer.

Semiconductor memory and method of manufacturing the semiconductor memory

A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region. The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.

A semiconductor memory device includes: a substrate including a first and a second regions; first wiring layers disposed in a first direction; a second wiring layer; a third wiring layer closer to the substrate than the first and the second wiring layers; a semiconductor film that penetrates the first and the second wiring layers, and is connected to the third wiring layer; and a gate insulating film disposed between the semiconductor film and the first wiring layers. The first wiring layers include first conductive films opposed to the semiconductor film in the first region, and first films in the second region. The second wiring layer includes a second conductive film opposed to the semiconductor film in the first region, and a second film in the second region. The second film is different from the first films.

According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.

Semiconductor device

A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second region overlapping the second portion and being a body different from the first region. The pedestal portion is provided in the second region. The plate portion contacts the pedestal portion and the first region. The first columnar portion includes a semiconductor layer. The semiconductor layer is adjacent to the plate portion with the stacked body interposed, and contacts the first region. The second columnar portion is adjacent to the plate portion with the stacked body interposed, and is adjacent to the pedestal portion with the second region interposed.

Three-dimensional memory device

Growing community of inventors

Kuwana, Japan

Yu Hirotsu