Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Hao Hu

Yi-Tzu Chen

Hao-I Yang

Geng-Cing Lin

Cheng-Jen Chang

Chia-Hao Hsu

A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.

Memory array and method of forming the same

A memory array includes a first column of memory cells, a second column of memory cells and a set of switching elements. The first column of memory cells includes a first bit line, a first word line and a second bit line. The second column of memory cells includes the second bit line, a second word line and a third bit line. The first and second column of memory cells are configured to share the second bit line. The first and second bit lines are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane. An amount of bit line switching elements in the set of bit line switching elements is equal to N*2, where N is an amount of columns of memory cells in the memory array.

A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.

Three-dimensional wordline sharing memory

A memory array includes a first memory column having a first bit line, a first word line and a second bit line. The memory array also includes a second memory column having the second bit line, a second word line and a third bit line. The first memory column and the second memory column are configured to share the second bit line. The sharing of the second bit line facilitates sharing one or more memory array components between the first memory column and the second memory column.

Apparatus and method for integrated circuit bit line sharing

A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines.

An apparatus and method for executing a write operation in a static random access memory (SRAM) array including memory cells that are coupled to a plurality of word lines and to a plurality of bit lines are provided. A clock signal is generated to start a write operation. A pulse is generated on the plurality of word lines in response to the clock signal. An operation voltage of the SRAM array is lowered for a period of time during the write operation. The period of time is controlled and the pulse is ended using a tracking circuit. The tracking circuit includes a plurality of tracking memory cells. The plurality of tracking memory cells have a timing characteristic that emulates a timing characteristic of the SRAM array during the write operation. The tracking circuit controls the period of time and ends the pulse based on the emulated timing characteristic.

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Kaohsiung, Taiwan

Yu-Hao Hu