Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Yu-Hao Hsu

Cheng Hung Lee

Chen-Lin Yang

Hung-Jen Liao

Yangsyu Lin

Yen-Huei Chen

Chiting Cheng

Jonathan Tsung-Yung Chang

Fu-An Wu

Jung-Ping Yang

Wei-Jer Hsieh

Zhi-Hao Chang

Chia-En Huang

Hidehiro Fujiwara

Wei Min Chan

Jui-Che Tsai

Chien-Chen Lin

Haruki Mori

Chia-Chen Kuo

Shih-Lien Linus Lu

Che-Ju Yeh

Tsung-Hsien Huang

Manish Arora

Nikhil Puri

Hektor Huang

Yi-Ching Chang

Hau-Tai Shieh

Chung-Yi Wu

Chien-Kuo Su

Shang-Chi Wu

Ming-Chien Tsai

Yih Wang

Chih-Yu Lin

Kao-Cheng Lin

Hao-I Yang

Cheng-Hung Lee

Hua-Hsin Yu

Chi-Ting Cheng

Chung-Hsien Hua

Zhi-hao Chang

Chen-Li Yang

Shan-Chi Yang

Tsung-Yuan Huang

Yang-Syu Lin

A bit line is pre-charged based on a clock signal internal to a bit line pre-charge circuit when a bit line pre-charge window is within a margin of a predetermined pre-charge window. A bit line is pre-charged based on a clock signal external to the bit line pre-charge circuit when the bit line pre-charge window is outside the margin of the predetermined pre-charge window.

Bit line pre-charge circuit and method

A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Memory device with word line pulse recovery

Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Voltage regulator with power rail tracking

A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.

SRAM with tracking circuitry for reducing active power

A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.

SRAM power-up random number generator

A memory circuit includes first and second memory segments coupled to first and second write lines, and first and second write line circuits coupled to the first and second write lines and configured to receive first and second data signals. The first and second data signals have complementary low and high logical states during a write operation to the first or second memory segment, and each of the first and second data signals has the low logical state during a masked write operation to the first or second memory segment. The first and second write line circuits output, to the first and second write lines, first and second write line signals responsive to the first and second data signals during the write operation and float the first and second data lines during the masked write operation.

Floating data line circuit and method

A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a word line driver connected to a word line, a row of memory cells connected to the word line, each memory cell powered by a first supply voltage, and a power circuit. The power circuit is configured to provide the first supply voltage to the word line driver when a read condition is satisfied, and a second supply voltage to the word line driver when the read condition is not satisfied, the second supply voltage being less than the first supply voltage.

Memory device and method of operating the same

A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal according to a first power supply signal from a first power supply and a status signal. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal, according to the first power management signal and the status signal.

Power management circuit, system-on-chip device, and method of power management

A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, an output node, first and second switching devices coupled in series between the output node and the power supply node, and a third switching device directly coupled to each of the output node and the reference node. The first switching device is configured to selectively couple the output node to the second switching device responsive to a first data signal, the second switching device is configured to selectively couple the first switching device to the power supply node responsive to a second data signal, and the third switching device is configured to selectively couple the output node to the reference node responsive to the first data signal.

Memory devices are disclosed that support multiple power ramping sequences or modes. For example, a level shifter device is operably connected to a memory macro in a memory device. The level shifter device receives at least one gating signal. Based on a state of the at least one gating signal, the level shifter device outputs one or more signals that cause or control voltage signals in or received by the memory macro to ramp up, ramp down, or ramp up and ramp down according to one or more power ramping modes.

Power ramping sequence control for a memory device

A memory device is disclosed. The memory device includes word lines, a tracking bit line and a word line driver. The word lines are configured to transmit word line signals to memory cells. The tracking bit line is coupled to a first plurality of tracking cells that are arranged in rows. The word line driver is coupled to the word lines and a control circuit that is coupled through the tracking bit line to the word lines. The word line driver is configured to control a falling edge of each of the word line signals, by receiving each corresponding tracking bit line signal of tracking bit line signals transmitted from the tracking bit line, based on a resistance of a length of the tracking bit line. The length is substantially distanced from each corresponding row of the rows to the control circuit. A method is also disclosed herein.

The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

Voltage supply selection circuit

Growing community of inventors

Tainan, Taiwan

Yu-Hao Hsu