Vanguard International Semiconductor Corporation

Yu-Hao Ho

Shin-Cheng Lin

Wen-Hsin Lin

Cheng-Tsung Wu

Shang-Hui Tu

Jui-Chun Chang

Chih-Jen Huang

Yu-Lung Chin

Shin-Chen Lin

Chiu-Hao Chen

Jian-Hsing Lee

Chien-Wei Chiu

Manoj Kumar

Yi-Hsiang Huang

Yeh-Jen Huang

Ting-You Lin

Chi-Li Tu

Hsiao-Ling Chiang

Li-Yang Hong

Yueh-Chu Chiang

A semiconductor device includes a gate electrode disposed on a substrate. A source region and a drain region are disposed in the substrate and located on two sides of the gate electrode respectively. The drain region includes a plurality of drain segments that are laterally separated from each other. These drain segments have a first conductive type and the substrate has a second conductive type. A plurality of drain contacts is electrically connected to the drain segments. Each drain segment corresponds to at least one of these drain contacts. A drain electrode is electrically connected to these drain contacts. A source electrode is electrically connected to the source region.

Semiconductor device

High-voltage semiconductor device and method of forming the same, the high-voltage semiconductor device includes a substrate, a gate structure, a drain, a first insulating structure and a drain doped region. The gate structure is disposed on the substrate. The drain is disposed in the substrate, at one side of the gate structure. The first insulating structure is disposed on the substrate, under the gate structure to partially overlap with the gate structure. The drain doped region is disposed in the substrate, under the drain and the first insulating structure, and the drain doped region includes a discontinuous bottom surface.

High-voltage semiconductor device and method of forming the same

A high-voltage semiconductor device includes a substrate, a body region, a well region, a bulk region, a source, a drain, an isolation region, a gate structure, and a resistor. The body region and the well region are disposed in the substrate. The bulk region and the source are disposed in the body region. The drain is disposed in the well region. The isolation region is disposed on the well region. The isolation region is disposed between the drain and the source. The gate structure is disposed on the substrate. The gate structure extends onto a portion of the isolation region. The resistor is disposed on the isolation region. The resistor is electrically connected to the bulk region and the drain, or the resistor is electrically connected to the drain and/or the source.

High-voltage semiconductor device

An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.

Lateral diffused metal oxide semiconductor field effect transistor

A semiconductor structure includes a substrate, a first insulating layer, a second insulating layer, a first seal ring structure, a second seal ring structure, and a passivation layer. The substrate has a chip region and a seal ring region. The first insulating layer is on the substrate. The second insulating layer is on the first insulating layer. The first seal ring structure is in the seal ring region and embedded in the first insulating layer and the second insulating layer, wherein the first seal ring structure includes a stack of metal layers. The second seal ring structure is in the seal ring region and embedded in the first insulating layer, wherein the second seal ring structure includes a polysilicon ring structure. The passivation layer is on the second insulating layer and the first seal ring structure.

Semiconductor structures

A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Method and apparatus for power device with multiple doped regions

A semiconductor structure is provided. A substrate has a first conductivity type. A first well and a second well are formed in the substrate. The first well has a second conductivity type. The second well has the first conductivity type. A doped region is formed in the first well and has the second conductivity type. A gate structure is disposed over the substrate and overlaps a portion of the first well and a portion of the second well. An insulating layer is disposed over the substrate and is spaced apart from the gate structure. A conducting wire is disposed on the insulating layer and includes a first input terminal and a first output terminal. The first input terminal is configured to receive an input voltage. The first output terminal is electrically connected to the doped region.

Semiconductor structure with a resistor and a transistor and method for forming the same

A semiconductor device includes a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein the buried layer has a dopant concentration that is greater than that of the semiconductor substrate. The semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, and a first element disposed on the first region of the semiconductor substrate, wherein the first element includes a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) transistor. In addition, the semiconductor device includes a second element disposed on the second region of the semiconductor substrate, wherein the second element includes an ultra-high voltage (UHV) transistor.

Semiconductor devices and methods for manufacturing the same

A semiconductor structure including a substrate, a first well, a first doped region, a second well, a second doped region, a field oxide, a first conductive layer, a first insulating layer and a second conductive layer is provided. Each of the substrate and the second well has a first conductivity type. The first and second wells are formed in the substrate. The first well has a second conductivity type. The first doped region is formed in the first well and has the second conductivity type. The second doped region is formed in the second well and has the first conductivity type. The field oxide is disposed on the substrate and is disposed between the first and second doped regions. The first conductive layer overlaps the field oxide. The first insulating layer overlaps the first conductive layer. The second conductive layer overlaps the first insulating layer.

Semiconductor structure having conductive layer overlapping field oxide

A semiconductor device includes a substrate, first and second body regions, a well region, a source region, a drain region, and first and second doped regions. The first and second body regions are disposed in first and second regions respectively. The well region is disposed in the first and second regions and between the first and second body regions. First and second portions of the source region are disposed in the first and second body regions respectively. The drain region is disposed on the well region. The first doped region is disposed in the well region. The second doped region is disposed on the first doped region. A first portion of the first doped region and a first portion of the second doped region are disposed in the well region of the first region and extend toward the first body region and out of the well region.

Semiconductor device and method for manufacturing the same

A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.

JFET and method for fabricating the same

A semiconductor structure is provided. A semiconductor substrate has a first conductivity type. A first well is formed in the semiconductor substrate and has a second conductivity type. A first well includes a first region and a second region. The dopant concentration of the first region is higher than the dopant concentration of the second region. A second well has the first conductivity type and is formed in the first region. A first doped region is formed in the first region and has the second conductivity type different than the first conductivity type. The second doped region has the first conductivity type and is formed in the second well. A third doped region has the first conductivity type and is formed in the second region. A fourth doped region has the second conductivity type and is formed in the first region.

Semiconductor structure and method of manufacturing the same

A high-voltage semiconductor device is provided. The device includes an epitaxial layer formed on a semiconductor substrate. The semiconductor substrate includes a first doping region having a first conductivity type. The epitaxial layer includes a body region that has a second conductivity type and a second doping region and a third doping region that have the first conductivity type. The second doping region and the third doping region are respectively on both opposite sides of the body region. A source region and a drain region are respectively in the body region and the second doping region. A gate structure is on the epitaxial layer. A fourth doping region having the second conductivity region is below the source region and adjacent to the bottom of the body region. The fourth doping region has a doping concentration greater than that of the body region.

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Yu-Hao Ho