Huawei Technologies Co., Limited

Schaeffler Technologies Ag & Co .kg

Alpha & Omega Semiconductor Corporation

Baoshan Iron & Steel Co., Ltd.

Yu Gong

Bingzhao Li

Yanyan Chen

Jingwei Chen

Yonghong Wang

Rui Gong

Hamza Yilmaz

Jun Lu

Yueh-Se Ho

Yan Xun Xue

Lei Liu

Zhiqiang Niu

Huawei Zhang

Hongxu Hei

Hong Fu

Yezhong Sun

Guo Feng Lian

Yaping Wu

A stator assembly and stator for a motor is provided that directly installs in a conductor slot a slot wedge having a width approximately the same as the width of the conductor slot. The slot wedge is limited in three directions, circumferential, radial, and axial, by means of cooperation between a slot wedge pressing ring, a conductor, and a sidewall of the conductor slot, and at the same time, the slot wedge is capable of preventing the conductor from falling out of the conductor slot. In addition, in the stator assembly for a motor disclosed, when the slot wedge is installed, the slot wedge may not only be inserted and installed in the conductor slot along the axial direction, but may also be inserted and installed in the conductor slot along the radial direction, and thus, the installation mode is flexible, which may improve the installation efficiency.

Stator assembly and stator for motor

Embodiments of the present invention disclose an image chip. The image chip includes: a processor for dividing an image frame into at least two image segments, a read circuit for reading the at least two image segments in a time-division manner, and an image synthesizer for successively performing image synthesis on the at least two image segments according to a time sequence read by the read circuit. The image frame comprises multiple layers and each layer in the multiple layers is a rectangular layer having two first boundaries. Two first boundaries of a first image segment in the at least two image segments correspond to two neighboring boundaries in all the first boundaries of the multiple layers. The image synthesis for each image segment in the at least two image segments comprises image synthesis for all sublayers in the each image segment.

Image synthesis method, image chip, and image device

The present application provides a method and a terminal for determining a frequency to be measured. The terminal receives frequency information about an inter-frequency measurement object and frequency priority information about the inter-frequency measurement object, and determines the number of at least one frequency for the received inter-frequency measurement object according to the frequency information, and when the number of the at least one frequency for the received inter-frequency measurement object is greater than the number of at least one frequency for an inter-frequency measurement object supported by the terminal, the terminal is capable of selecting, according to the frequency priority information, at least one frequency to be measured from the at least one frequency for the received inter-frequency measurement object, wherein the number of the at least one frequency to be measured is equal to the number of frequencies for the inter-frequency measurement object supported by the terminal.

Method and terminal for determining frequency to be measured

Embodiments of the present invention disclose an image synthesis method, an image chip, and an image device. The method includes separately obtaining two coordinates, on a first coordinate axis, corresponding to two boundaries that are of each layer in multiple layers of an image frame and that are perpendicular to the first coordinate axis, so as to obtain multiple coordinates corresponding to the multiple layers. The method also includes dividing, by using the multiple coordinates, the image frame into at least two image segments perpendicular to the first coordinate axis; reading, along a direction of the first coordinate axis, the at least two image segments in a time-division manner and according to a scanning sequence. Additionally, the method includes successively performing image synthesis on the at least two image segments according to a time sequence of reading the at least two image segments, so as to generate display data.

A hot rolled silicon steel producing method comprises: silicon steel slab heating process, rough rolling process and finish rolling process. The heating process comprises a pre-heating stage, a heating stage and a soaking stage. The pre-heating stage satisfies the following formula (1). In the formula, VTp is a temperature increasing rate, in the pre-heating stage, whose unit is &#xb0; C./min; t is a total heating time of the slab in the heating furnace, and t=180-240 min; and Tc is an initial temperature when the slab is put into the furnace, whose unit is &#xb0; C. By using the foregoing formula, the heating process and the rough rolling process are changed, an occurrence rate of edge defects during the production of the hot rolled silicon steel can be reduced, and the hot rolled silicon steel with good surface quality can be produced. 

Hot rolled silicon steel producing method

A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick metal layer at bottom surface of wafer in recessed space in a sequence; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and the metal seed and metal layers along the scribe line.

Wafer process for molded chip scale package (MCSP) with thick backside metallization

Growing community of inventors

Shanghai, China

Yu Gong