Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Yu-Fan Lin

Shin-Jang Shen

Perng-Fei Yuh

Shao-Ting Wu

Jih-Chen Wang

Caleb Yu-Sheng Cho

Yih Wang

Yu-Der Chih

Meng-Fan Chang

Ku-Feng Lin

Tung-Cheng Chang

Meng-Fan Cheng

Yu-Der Chen

A memory circuit includes a memory array comprising a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines that extend along a lateral direction. The memory circuit includes a first access circuit physically disposed on a first side of the memory array in the lateral direction. The memory circuit includes a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side. When each of the non-volatile memory cells is configured to be programmed by at least a first current and a second current, the first current and second current flow through a first path and a second path, respectively. The first path at least comprises a portion on the first side and the second path at least comprises a portion on the second side.

Memory devices with dual-side access circuits and methods for operating the same

A memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage. The memory circuit includes a plurality of voltage clamp devices coupled to the plurality of second buffers, and each voltage clamp device is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.

Memory circuit and method of operating the same

A bias voltage generator includes a first current path, a first voltage clamp device, and a first buffer. The bias voltage generator receives a reference voltage and generates a first bias voltage based on a voltage difference between the reference voltage and a first drive voltage, the first voltage clamp device generates the first drive voltage based on the first bias voltage by applying the first drive voltage to the first current path, and the first buffer receives the first bias voltage and generates a second bias voltage based on the first bias voltage. A second current path includes a resistance-based memory device, and a second voltage clamp device generates a second drive voltage based on the second bias voltage and applies the second drive voltage to the second current path.

A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted V) to the sense enable sub-circuit. The sense enable sub-circuit is configured to adjust the received voltage based on the sensed value of bit lines and sends the adjusted voltage to the sense output sub-circuit. The sense output sub-circuit removes interference, inverts and amplifies the adjusted voltage, and sends an output voltage to the buffer sub-circuit. The buffer sub-circuit amplifies the output voltage of the sense output sub-circuit and provides it to an output bus.

Apparatus and method for sense amplifying

A low-offset current-sense amplifier and an operating method thereof are disclosed. The low-offset current-sense amplifier includes a sense amplifier, a first current supply unit, a second current supply unit, and a processing unit. The first current supply unit is coupled to the sense amplifier, and includes a first transistor group and a first current output terminal. The second current supply unit is coupled to the sense amplifier, and includes a second transistor group and a second current output terminal. The processing unit controls the on/off of some transistors of the first transistor group and the second transistor group according to electric currents output from the first current output terminal and the second current output terminal, respectively.

Low-offset current-sense amplifier and operating method thereof

A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.

Growing community of inventors

Hsinchu, Taiwan

Yu-Fan Lin