Intel Corporation

Alibaba Group Holding Limited

Yu Du

Xin Guo

Shu Li

David J Pelster

Ping Zhou

Aliasgar S Madraswala

Yogesh B Wakchaure

Purval Shyam Sule

David B Carlton

Donia Sebastian

Naveen Prabhu Vittal Prabhu

Fei Liu

Curtis A Gittens

Ryan J Norton

Sheng Qiu

Sudhakar Ayyasamy

Mark Anthony S Golez

One embodiment facilitates measurement of a performance of a storage device. During operation, the system determines a normalized cost for an I/O request, wherein the normalized cost is independent of an access pattern and a type of the I/O request, wherein the normalized cost is indicated by a first number of virtual I/O operations consumed by the I/O request, and wherein a virtual I/O operation is used as a logical unit of cost associated with physical I/O operations. The system identifies a performance metric for the storage device by calculating a second number of virtual I/O operations per second which can be executed by the storage device. The system allocates incoming I/O requests to the storage device based on the performance metric, e.g., to satisfy a Quality of Service requirement, thereby causing an enhanced measurement of the performance of the storage device.

System and method for managing resources of a storage device and quantifying the cost of I/O requests

Disclosed are systems, methods, and apparatuses for providing a high-speed data path to storage devices. In one embodiment, a method is disclosed comprising receiving, by the processor, a data access command, the data access command specifying a location in memory to access data; issuing, by the processor, the data access command to the storage device via a first datapath, the first datapath comprising a non-block datapath; and accessing, by the processor, the non-volatile storage component through the first datapath and the memory, wherein the non-volatile storage component of the storage device is mapped to memory accessible by the processor.

Rapid side-channel access to storage devices

An embodiment of a semiconductor apparatus may include technology to determine a differentiator associated with an access request for two or more memory devices, and set a target order for the two or more memory devices based on the differentiator. Other embodiments are disclosed and claimed.

Ordering of memory device mapping to reduce contention

Provided are an apparatus, system and method for apparatus, system and method for throttling an acceptance rate for adding host Input/Output (I/O) commands to a buffer in a non-volatile memory storage device. Information is maintained on an input rate at which I/O commands are being added to the buffer and information is maintained on an output rate at which I/O commands are processed from the buffer to apply to execute against the non-volatile memory. A determination is made of a current level of available space in the buffer and an acceptance rate at which I/O commands are added to the buffer from the host system to process based on the input rate, the output rate, the current level of available space, and an available space threshold for the buffer to maintain the buffer at the available space threshold. I/O commands are added to the buffer to process based on the acceptance rate. The I/O commands are accessed from the buffer to process to execute against the non-volatile memory.

Apparatus, system and method for throttling a rate at which commands are accepted in a storage device

A reduction in Quality of Service (QoS) latency for host read commands in a power limited operation mode in a storage device is provided. A priority level is assigned to a host command using weighted round robin arbitration. Power resources are allocated based on the priority levels assigned to host commands to minimize host read command latency in the power limited operation mode.

Method and apparatus to prioritize read response time in a power-limited storage device

Technology to dynamically modulate read granularity of a memory device. A computing system may include a controller and one or more memory devices coupled to the controller, the one or more memory devices including instructions, which when executed by the controller, may cause the computing system to determine whether a read to a memory device satisfies a sub-page read policy. In addition, the instructions, when executed, may cause the computing system to issue a sub-page read command to retrieve data from the memory device at sub-page granularity when the read satisfies the sub-page read policy. Moreover, the instructions, when executed, may cause the computing system to issue a full-page read command to retrieve the data at full-page granularity when the read does not satisfy the sub-page read policy or when a read for a segment of sequentially stored data does not satisfy the sub-page read policy.

Technology to dynamically modulate memory device read granularity

In one embodiment, an apparatus comprises a memory array and a controller. The controller is to receive a first read command specifying a read voltage offset profile identifier; identify a read voltage offset profile associated with the read voltage offset profile identifier, the read voltage offset profile comprising at least one read voltage offset; and perform a first read operation specified by the first read command using at least one read voltage adjusted according to the at least one read voltage offset of the read voltage offset profile.

Growing community of inventors

Santa Clara, CA, United States of America

Yu Du