Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Yu-Der Chih

Chia-Fu Lee

Yi-Chun Shih

Chung-Cheng Chou

Hon-Jarn Lin

Ku-Feng Lin

Shih-Lien Linus Lu

Jonathan Tsung-Yung Chang

Zheng-Jun Lin

Chien-Yin Liu

Shao-Yu Chou

Hsueh-Chih Yang

Po-Hao Lee

Chen-Ming Hung

Hung-Chang Yu

Yen-An Chang

Wen-Ting Chu

Ya-Chin King

Kai-Chun Lin

Kuan-Chun Chen

Yun-Sheng Chen

Chin-I Su

Yuhsiang Chen

Yih Wang

Jam-Wem Lee

Hiroki Noguchi

Jen-Chou Tseng

Yu-Ti Su

Ming-Hsiang Song

Chrong Jung Lin

Meng-Chun Shih

Ching-Huang Wang

Chun-Hao Chang

Min-Shin Wu

Shu-Chuan Lee

Chien-An Lai

Meng-Fan Chang

Cheng-Hsiung Kuo

Gu-Huan Li

Pei-Ling Tseng

Chung-Chieh Chen

May-Be Chen

Randy B Osborne

Win-San Khwa

Chun-Jung Lin

Cheng-En Lee

Kun-Hsi Li

Jonathan Tehan Chen

Chi-Hsiang Weng

Win San Khwa

Shih-Liang Wang

C Y Wang

Hsin-Yuan Yu

Wen Zhang Lin

Hidehiro Fujiwara

William Joseph Gallagher

Tong-Chern Ong

Yu-Lin Chen

Cheng-Xin Xue

Chieh-Pu Lo

Je-Syu Liu

Maybe Chen

Harry-Hak-Lay Chuang

Yen-Huei Chen

Burn Jeng Lin

Ying-Hao Kuo

Jui-Jen Wu

Chrong-Jung Lin

Tien-Wei Chiang

Shin-Jang Shen

Hsu-Shun Chen

Wei-Chang Zhao

Chieh Lee

Haruki Mori

Yu-Fan Lin

Chi-Tsai Chen

Yi-Chieh Chiu

Wen-Zhang Lin

Saman Adham

Wenhsien Kuo

Chien-Ye Lee

Tun-Fei Chien

Chi-Fu Lee

Cheng-Jun Lin

Wang-Yi Lee

Chun-Yun Wu

Bo Yu Lin

Cy Wang

Jenn-Jou Wu

In some aspects of the present disclosure, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subgroup of FAs, wherein each FA of the first subgroup includes a first number of transistors; and a second subgroup of FAs, wherein each FA of the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subgroup receives a first input from a first one of the second subgroup of FAs and a second input from a second one of the second subgroup of FAs, and each FA provides a first output to a third one of the second subgroup of FAs and a second output to a fourth one of the second subgroup of FAs.

Low power adder tree structure

A semiconductor fabrication apparatus and a method of using the same are disclosed. In one aspect, the apparatus includes a holder configured to place a substrate and a radiation source configured to provide radiation to transfer a pattern onto the substrate. The apparatus also includes a plurality of sensing devices configured to provide a reference signal based on an intensity of the radiation when the substrate is not present. The apparatus further includes a controller, operatively coupled to the plurality of sensing devices, configured to adjust the intensity of the radiation based on the reference signal.

Semiconductor fabrication apparatus and method of using the same

A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.

RRAM voltage compensation

A memory device includes a column of at least three memory cells and a source line coupled to the source terminal of each memory cell. A source line driver is coupled to the source line, a voltage terminal, and a program voltage source and is switchable between a program operation, an erase operation, and a read operation.

Memory device in which latch is coupled to source line and method of operation

A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

MRAM reference current

Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.

Integrated circuit (IC) signatures with random number generator and one-time programmable device

A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the second column of memory cells.

Memory cell array circuit and method of forming the same

A memory device includes a first active area, a first doped structure of a first doping type, a second active area, a first gate structure and a second doped structure of a second doping type different from the first doping type. The second active area is disposed between the first active area and the first doped structure. The first gate structure is disposed between the first active area and the second active area in a layout view, and configured to store a first bit with the first active area and the second active area. The second doped structure is coupled to the first gate structure and disposed between the first doped structure and the second active area. The second doped structure and the first doped structure are configured to receive a first signal corresponding to the first bit from the first gate structure.

Memory device and system

A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.

Resistive memory with low voltage operation

A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Resistive random access memory device

An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.

SRAM-based cell for in-memory computing and hybrid computations/storage memory architecture

A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.

Semiconductor device and operation method thereof

A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Low-dropout (LDO) regulator with a feedback circuit

Methods for reading a memory are provided. In response to a first address signal, a first signal is obtained according to first data of the memory and a second signal is obtained according to second data of the memory by a decoding circuit. Binary representation of the first signal is complementary to that of the second signal. A first sensing signal is provided according to a reference signal and the first signal and a second sensing signal is provided according to the reference signal and the second signal by a sensing circuit. An output corresponding to the first sensing signal or the second sensing signal is output in response to a control signal, by an output buffer.

Method for reading memory

A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bit-line.

One time programmable memory

Growing community of inventors

Hsinchu, Taiwan

Yu-Der Chih