Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Yu-Der Chih

Chia-Fu Lee

Yi-Chun Shih

Chung-Cheng Chou

Hon-Jarn Lin

Jonathan Tsung-Yung Chang

Ku-Feng Lin

Shih-Lien Linus Lu

Zheng-Jun Lin

Chien-Yin Liu

Shao-Yu Chou

Hsueh-Chih Yang

Po-Hao Lee

Chen-Ming Hung

Hung-Chang Yu

Ya-Chin King

Yun-Sheng Chen

Yen-An Chang

Wen-Ting Chu

Chrong Jung Lin

Kai-Chun Lin

Kuan-Chun Chen

Chin-I Su

Yuhsiang Chen

Yih Wang

Jam-Wem Lee

Hiroki Noguchi

Yu-Ti Su

Jen-Chou Tseng

Ming-Hsiang Song

Ching-Huang Wang

Meng-Chun Shih

Chun-Hao Chang

Min-Shin Wu

Chien-An Lai

Shu-Chuan Lee

Meng-Fan Chang

Cheng-Hsiung Kuo

Gu-Huan Li

Pei-Ling Tseng

Chung-Chieh Chen

Wen Zhang Lin

Hsin-Yuan Yu

May-Be Chen

Randy B Osborne

Win-San Khwa

Chun-Jung Lin

Cheng-En Lee

Kun-Hsi Li

Jonathan Tehan Chen

Chi-Hsiang Weng

Win San Khwa

Shih-Liang Wang

C Y Wang

Wang-Yi Lee

Maybe Chen

Hidehiro Fujiwara

William Joseph Gallagher

Chrong-Jung Lin

Tong-Chern Ong

Yu-Lin Chen

Cheng-Xin Xue

Chieh-Pu Lo

Wen-Zhang Lin

Je-Syu Liu

Cheng-Jun Lin

Harry-Hak-Lay Chuang

Yen-Huei Chen

Burn Jeng Lin

Ying-Hao Kuo

Jui-Jen Wu

Tien-Wei Chiang

Shin-Jang Shen

Wei-Chang Zhao

Hsu-Shun Chen

Haruki Mori

Chieh Lee

Yu-Fan Lin

Chi-Tsai Chen

Yi-Chieh Chiu

Saman Adham

Wenhsien Kuo

Chien-Ye Lee

Cy Wang

Chi-Fu Lee

Tun-Fei Chien

Chun-Yun Wu

Jenn-Jou Wu

Bo Yu Lin

A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.

Resistive random access memory based one-time-programmable memory devices

A semiconductor device includes a plurality of memory cells, a first reference cell connected to a first subset of the plurality of memory storage cells via a first common source line, and a second reference cell connected to a second subset of the plurality of memory storage cells via a second common source line. The semiconductor device also includes a sense amplifier configured to, when reading from a first memory cell of the first subset, receive an output from the second reference cell and an output from the first memory cell.

Semiconductor device including reference cells and a method of operating thereof

Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Memory cell including programmable resistors with transistor components

A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

Resistive memory device with protrusion covered with resistance changing element and method for manufacturing the same

In some aspects of the present disclosure, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subgroup of FAs, wherein each FA of the first subgroup includes a first number of transistors; and a second subgroup of FAs, wherein each FA of the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subgroup receives a first input from a first one of the second subgroup of FAs and a second input from a second one of the second subgroup of FAs, and each FA provides a first output to a third one of the second subgroup of FAs and a second output to a fourth one of the second subgroup of FAs.

Low power adder tree structure

A semiconductor fabrication apparatus and a method of using the same are disclosed. In one aspect, the apparatus includes a holder configured to place a substrate and a radiation source configured to provide radiation to transfer a pattern onto the substrate. The apparatus also includes a plurality of sensing devices configured to provide a reference signal based on an intensity of the radiation when the substrate is not present. The apparatus further includes a controller, operatively coupled to the plurality of sensing devices, configured to adjust the intensity of the radiation based on the reference signal.

Semiconductor fabrication apparatus and method of using the same

A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.

RRAM voltage compensation

A memory device includes a column of at least three memory cells and a source line coupled to the source terminal of each memory cell. A source line driver is coupled to the source line, a voltage terminal, and a program voltage source and is switchable between a program operation, an erase operation, and a read operation.

Memory device in which latch is coupled to source line and method of operation

A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

MRAM reference current

Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.

Integrated circuit (IC) signatures with random number generator and one-time programmable device

A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the second column of memory cells.

Memory cell array circuit and method of forming the same

A memory device includes a first active area, a first doped structure of a first doping type, a second active area, a first gate structure and a second doped structure of a second doping type different from the first doping type. The second active area is disposed between the first active area and the first doped structure. The first gate structure is disposed between the first active area and the second active area in a layout view, and configured to store a first bit with the first active area and the second active area. The second doped structure is coupled to the first gate structure and disposed between the first doped structure and the second active area. The second doped structure and the first doped structure are configured to receive a first signal corresponding to the first bit from the first gate structure.

Memory device and system

A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.

Resistive memory with low voltage operation

A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Resistive random access memory device

An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.

SRAM-based cell for in-memory computing and hybrid computations/storage memory architecture

Growing community of inventors

Hsinchu, Taiwan

Yu-Der Chih