Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Chung Su

Ching-Yu Chang

Teng-Chun Tsai

Wen-Yun Wang

Chin-Hsiang Lin

Chung-Wei Hsu

Kuei-Shun Chen

Shen-Nan Lee

Chia-Chu Liu

Chen-Hao Wu

Yahru Cheng

Chi-Kang Chang

Tsung-Ling Tsai

Ying-Hao Su

Yu-Lun Liu

Tai-Chun Huang

Cheng-Han Wu

Yen-Chun Huang

Joy Cheng

Wen-Kuei Liu

Ting-Ting Chen

Kao-Feng Liao

Kuan-Hsin Lo

Yu-Ting Yen

Chun-Chih Ho

Ling-Fu Nieh

Pin-Chuan Su

A method of forming a semiconductor device includes forming a plurality of non-insulator structures on a substrate, the plurality of non-insulator structures being spaced apart by trenches, forming a sacrificial layer overfilling the trenches, reflowing the sacrificial layer at an elevated temperature, wherein a top surface of the sacrificial layer after the reflowing is lower than a top surface of the sacrificial layer before the reflowing, etching back the sacrificial layer to lower the top surface of the sacrificial layer to fall below top surfaces of the plurality of non-insulator structures, forming a dielectric layer on the sacrificial layer, and removing the sacrificial layer to form air gaps below the dielectric layer.

Air gap formation method

A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.

Method for forming multi-layer mask

In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.

Anti-reflective coating materials

In a method of manufacturing a semiconductor device, a photo resist layer is formed over a substrate with underlying structures. The first photo resist layer is exposed to exposure radiation. The exposed first photo resist layer is developed with a developing solution. A planarization layer is formed over the developed photo resist layer. The underlying structures include concave portions, and a part of the concave portions is not filled by the developed first photo resist.

Method for manufacturing a semiconductor device

A method includes providing a photoresist solution that includes a first solvent having a first volume and a second solvent having a second volume, where the first solvent is different from the second solvent and where the first volume is less than the second volume; dispersing the photoresist solution over a substrate to form a film, where the dispersing evaporates a portion of the first solvent and a portion of the second solvent such that a remaining portion of the first solvent is greater than a remaining portion of the second solvent; baking the film; after baking the film, exposing the film to form an exposed film; and developing the exposed film.

Resist solvents for photolithography applications

Anti-reflective gap filling materials and methods

Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.

Method and structure for gap filling improvement

A method includes forming a spin-on carbon (SOC) layer over a target structure; chemically treating an upper portion of the SOC layer; forming a sacrificial layer over the SOC layer; performing a chemical mechanical polish (CMP) process on the sacrificial layer until reaching the SOC layer, wherein the chemically treated upper portion of the SOC layer has a higher resistance to the CMP process than that of the sacrificial layer; forming a patterned photoresist layer over the SOC layer after the CMP process; and etching the target structure using the patterned photoresist layer as a mask.

Polymer resin comprising gap filling materials and methods

An anti-reflective coating (ARC) composition for use in lithography patterning and a method of using the same is disclosed. In an embodiment, the ARC composition comprises a polymer having a chromophore; an acid labile group (ALG), more than 5% by weight; a thermal acid generator; and an optional crosslinker. The method includes applying the ARC composition over a substrate; crosslinking the polymer to form an ARC layer; cleaving the ALG of the ARC layer to reduce a film density of the ARC layer; forming a resist layer over the ARC layer, patterning the resist layer, and etching the ARC layer. Due to reduced film density, the ARC layer has a high etching rate, thereby preserving the critical dimension (CD) of the resist pattern during the etching process.

Composition and method for lithography patterning

FinFET structures and methods of forming the same are disclosed. In a method, a recess is formed exposing a plurality of semiconductor fins on a wafer. A dummy contact material is formed in the recess. The dummy contact material contains carbon. The dummy contact material is cured with one or more baking steps. The one or more baking steps harden the dummy contact material. A first portion of the dummy contact material is replaced with an inter-layer dielectric. A second portion of the dummy contact material is replaced with a plurality of contacts. The plurality of contacts are electrically coupled to source/drain regions of the plurality of semiconductor fins.

FinFET structures and methods of forming the same

The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.

Gap filling materials and methods

A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating component in order to form a floating region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating component may be a floating cross-linking agent, a floating polymer resin, or a floating catalyst. The floating cross-linking agent, the floating polymer resin, or the floating catalyst may comprise a fluorine atom.

Anti-reflective layer and method

The present disclosure provides a method that includes forming a polymeric material layer on a substrate, wherein the polymeric material layer includes de-crosslinkable crosslink material (DCM); performing a first baking process having a first baking temperature to the polymeric material layer, thereby initiating crosslinking function of the DCM; and performing a second baking process having a second baking temperature to the polymeric material layer, thereby initiating de-crosslinking function of the DCM.

Growing community of inventors

Hsinchu, Taiwan

Yu-Chung Su