Sandisk Technologies Inc.

Micron Technology Incorporated

Western Digital Technologies, Inc.

Yu-Chung Lien

Huai-Yuan Tseng

Zhenming Zhou

Deepanshu Dutta

Jiahui Yuan

Tomer Eliash

Xue Bai Pitner

Xiang Yang

Ching-Huang Lu

Hua-Ling Cynthia Hsu

Ravi J Kumar

Sarath Chandran Puthenthermadam

Murong Lang

Fanglin Zhang

Sujjatul Islam

Christopher John Petti

Mark Murin

Abhijith Prakash

Li-Te Chang

Juan Lee

Keyur Payak

Eran Sharon

Alexander Bazarsky

Henry Chin

Jun Wan

Ken Oowada

Dengtao Zhao

Michael G Miller

Bo Lei

Wei Wang

Tai-Yuan Tseng

Shinsuke Yada

Mark Shlick

Juane Li

Tomer Tzvi Eliash

Ohwon Kwon

Sead Zildzic, Jr

Swaroop Kaza

Vinh Q Diep

Erika Penzo

Fanqi Wu

Zhenni Wan

Zhuojie Li

Vivek Shivhare

Kazuki Isozumi

Michael Huai-Yuan Tseng

Kai Kirk

Methods, systems, and apparatuses include determining to apply a read retry operation to a portion of memory. The likelihood of a read retry timeout meeting a threshold is determined. A reverse trim setting is selected in response to determining the likelihood of the read retry timeout meets the threshold. The read retry operation is executed using the selected trim setting.

Dynamic read retry voltage sequences in a memory subsystem

In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Memory read operation using a voltage pattern based on a read command type

Implementations described herein relate to a memory device with a fast write mode to mitigate power loss. In some implementations, the memory device may detect a condition associated with power supplied to the memory device. The memory device may detect one or more pending write operations to be performed to cause data to be written to memory cells of the memory device. The memory device may switch from a first voltage pattern, previously used by the memory device to write data to one or more memory cells of the memory device, to a second voltage pattern based on detecting the condition and based on detecting the one or more pending write operations. The memory device may perform at least one write operation, of the one or more pending write operations, using the second voltage pattern.

Memory device with fast write mode to mitigate power loss

A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.

CELSRC voltage separation between SLC and XLC for SLC program average ICC reduction

A first page read on the first memory page utilizing a first trim value is performed responsive to initiating a memory page scan on a first memory page of a plurality of memory pages. Whether a first data state metric associated with the first page read satisfies a first threshold criterion is determined. A second page read on the first memory page utilizing a second trim value is performed responsive to determining that the first data state metric satisfies the first threshold criterion. Whether a second data state metric associated with the second page read satisfies a second threshold criterion is determined. The second trim value to perform subsequent page reads during memory page scans is selected responsive to determining that the second data state metric does not satisfy the first threshold criterion.

Dynamic read level trim selection for scan operations of memory devices

Methods, systems, and apparatuses include determining an operation type for an operation. A sensing time is elected using the operation type. The operation is executed using the sensing time.

Adaptive sensing time for memory operations

A memory subsystem receives a first read command and a second read command. Responsive to determining that the first read command originated from a host system, the memory subsystem selects a reverse read trim setting. Responsive to determining that the second read command did not originate from the host system, the memory subsystem selects a forward read trim setting. The memory subsystem executes the first read command using the reverse read trim setting. The memory subsystem executes the second read command using the forward read trim setting.

Management of dynamic read voltage sequences in a memory subsystem

A method includes determining that a program operation includes a first pass to apply a first voltage distribution to a plurality of memory cells and a second pass to apply a second voltage distribution to the plurality of memory cells, performing the first pass of the program operation using a first sensing time, and performing the second pass of the program operation using a second sensing time during the second pass of the program operation, where the first sensing time is shorter than the second sensing time.

Independent sensing times

Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A bitline voltage is determined using the cycle number and the group. The command is executed using the bitline voltage.

Adaptive bitline voltage for memory operations

A program command specifying new data to be programmed is received and partitioned into a plurality of data partitions. A wordline addressing a first set of memory cells to be programmed with a data partition of the plurality of data partitions is identified for a specified block of the memory device. Existing data stored by a second set of memory cells is read. An expected data state metrics is produced for each data partition of the plurality of data partitions. A data partition associated with a lowest expected data state metric among the plurality of expected data state metrics is identified. The identified data partition is programmed to the identified wordline.

Charge loss mitigation through dynamic programming sequence

An apparatus that includes a set of memory components of a memory sub-system is provided. The set of memory components include a first memory block comprising first units of linearly arranged memory cells and a second memory block comprising second units of linearly arranged memory cells. The set of memory components include a slit portion dividing the first and second memory blocks. The slit portion includes a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells.

3D NAND memory with built-in capacitor

A memory device that includes a plurality of memory cells arranged in an array is provided. A control circuitry is configured to program a single bit of data in each memory cell of the plurality of memory cells. The control circuitry is further configured to program a first set of memory cells of the plurality of memory cells using a first programming operation that includes a single programming pulse and no verify pulse and program a second set of memory cells of the plurality of memory cells using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.

Memory programming techniques to reduce power consumption

Apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. The set of memory components includes a processing device that initiates a corrective read (CR) operation on a set of memory components. The set of memory components includes a pillar that includes a channel and a plurality of transistors. The processing device applies a charge to a first word line (WL) comprising a first transistor of a plurality of transistors to neutralize charges in the channel and senses a charge distribution of a second WL comprising a second transistor of the plurality of transistors adjacent to the first transistor based on the charge applied to the first WL that neutralized the charges in the channel.

3D NAND memory with fast corrective read

A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device. The processing device is further to determine a value of a metric reflecting a state of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a programming operation with respect to the subset of memory cells. The programming operation includes the delay between a first pass of the programming operation and a second pass of the programming operation.

Adaptive programming delay scheme in a memory sub-system

Implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. In some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. The memory device may set a flag value based on comparing a transition time and a transition time threshold. The transition time may be a time to transition from a first voltage to a second voltage during the program operation. The memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.

Detecting a memory write reliability risk without using a write verify operation

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San Jose, CA, United States of America

Yu-Chung Lien