United Microelectronics Corp.

Yu-Chun Chang

Ping-Chia Shih

Chi-Cheng Huang

Hsiang-Chen Lee

Kuo-Lung Li

Kun-I Chou

Wan-Fang Chung

Je-Yi Su

Chia-Wen Wang

Ling-Hsiu Chou

Chung-Che Huang

Meng-Chun Chen

Chih-Yang Hsu

Chia-Cheng Hsu

Jheng-Jie Huang

Mu-Jia Liu

Tseng-Fang Dai

The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S) removing the part of the U-shaped ONO structure; (S) removing the photoresist; (S) removing the pad oxide pattern and the top oxide layer; and (S) forming a gate structure.

Method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell

A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Method for fabricating semiconductor device including a patterned multi-layered dielectric film with an exposed edge

A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.

Method for fabricating semiconductor device

A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.

Semiconductor device and fabrication method thereof

A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.

Method for manufacturing silicon&#x2014;oxide&#x2014;nitride&#x2014;oxide&#x2014;silicon (SONOS) non-volatile memory cell

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Taichung, Taiwan

Yu-Chun Chang