Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

Au Optronics Corporation

Auo Corporation

Nyquest Corporation Limited

Yu-Chu Chen

Wen-Juh Kang

Ting-Hao Wang

Hsin-Han Han

Wei-Ting Chen

Chen-Yang Pan

Yi-Lin Lee

Chun-Hui Huang

Yi-Hsiang Hu

Hsun-Wei Kao

Man-Pio Lam

Yu-Chi Kang

Kuan-Jung Chen

Cheng-Hung Wu

Hua-Shih Liao

Po Chun Lin

Shao-Hua Wan

Chih-Hsuan Lee

An arcuate display device, including an arcuate display surface, a plurality of display units, an image source, and a controller, is provided. The display units are configured on the arcuate display surface in an array manner, and each of the display units includes a plurality of pixels. The controller is configured to receive a plurality of pixel signals from the image source to generate a plurality of frame signals respectively corresponding to the display units. Each of the frame signals includes the pixel signals, a plurality of first dummy signals, and a plurality of second dummy signals, in which the pixel signals respectively correspond to the pixels. A sum of an amount of the pixel signals, an amount of the first dummy signals, and an amount of the second dummy signals in each of the frame signals is same. A driving method of the arcuate display device is also provided.

Arcuate display device and driving method thereof

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a controlling circuit. The ADC circuits are configured to generate first quantized outputs according to clock signals. The calibration circuit is configured to perform at least one error operation according to the first quantized outputs to generate second quantized outputs, and is configured to analyze time difference information of the clock signals according to the second quantized outputs to generate adjustment signals. The controlling circuit is configured to analyze the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is configured to control the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.

Analog to digital converter device and method for controlling calibration circuit

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a skew adjusting circuit. The ADC circuits convert an input signal according to clock signals, to generate first quantized outputs. The calibration circuit calibrates the first quantized outputs to generate second quantized outputs. The skew adjusting circuit includes an estimating circuit and a feedback circuit. The estimating circuit analyzes the second quantized outputs to generate detection signals, wherein the detection signals are related to time difference information of the clock signals. The skew adjusting circuit outputs the detection signals as adjustment signals, wherein the adjustment signals are configured to reduce a clock skew of the ADC circuits. The feedback circuit analyzes the detection signals generated by the estimating circuit, to generate a feedback signal to the estimating circuit, wherein the estimating circuit is configured to adjust the detection signals according to the feedback signal.

Analog to digital converter device and method for calibrating clock skew

A display device is provided. The display device includes a panel, a memory, and a controller. The panel includes multiple pixels. The memory includes a first section and a second section. The memory stores an aging record table. Multiple brightness attenuation values recorded in the aging table are respectively divided into multiple first portion attenuation values and multiple second portion attenuation values. The first section stores the first portion attenuation values. The second section stores the second portion attenuation values. The controller includes an update circuit and a compensation circuit. The controller is coupled to the panel and the memory. The update circuit receives gray values displayed by the pixels to update the aging table. The compensation circuit reads the first portion attenuation values from the first section so as to perform an aging compensation on the pixels.

Display device

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits are configured to convert an input signal according to interleaved clock signals to generate first quantized outputs. The calibration circuit is configured to perform at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit further includes a first adjusting circuit. The first adjusting circuit is configured to analyze adjacent clock signals according to part of the second quantized outputs to generate adjusting information. The skew adjusting circuit is configured to analyze time difference information within even-numbered sampling periods of the clock signals according to the second quantized outputs and the adjusting information to generate adjustment signals. The adjustment signals are configured to reduce clock skews of the ADC circuits.

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration computation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit determines calculating signals, to which the second quantized outputs correspond in a predetermined interval, and averages the calculating signals to generate a reference signal, and compares the reference signal with each of the calculating signals to generate detecting signals, and determines whether the detecting signals are adjusted or not according to a signal frequency to generate adjusting signals, in order to reduce a clock skew in the ADC circuits.

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration computation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit determines maximum value signals, to which the second quantized outputs correspond in a predetermined interval, and averages the maximum value signals to generate a reference signal, and compares the reference signal with each of the maximum value signals to generate detecting signals, and determines whether the detecting signals are adjusted or not according to a signal frequency to generate adjusting signals, in order to reduce a clock skew in the ADC circuits.

An analog-to-digital converting system includes multiple stages of analog-to-digital converters (ADCs) and a skew calibration circuit. The multiple stages of ADCs are configured to sample a test signal according to multiple interleaved clock signals, respectively, so as to respectively generate multiple stages of quantized outputs. The analog-to-digital converting system has a sampling frequency resulting from operations of the multiple stages of ADCs. The test signal has a first frequency and the sampling frequency is N times the first frequency, and N is an odd number larger than 1. The skew calibration circuit is configured to sequentially analysis, for every N stages, the multiple stages of quantized outputs to generate multiple digital codes. The skew calibration circuit is further configured to calibrate a time skew of the analog-to-digital converting system according to a comparison result between the multiple digital codes and a reference code.

Analog to digital converting system, time-skew calibration method, and related computer program product

A communication receiving device includes a clock data recovery circuit, an analog-to-digital converter (ADC), a channel evaluating circuit, a first equalizer, and a selector. The clock data recovery circuit is configured to generate a clock signal according to a first digital signal. The ADC is coupled to the clock data recovery circuit, and configured to convert a first analog signal to a second digital signal according to the clock signal. The channel evaluating circuit is configured to analyze the second digital signal to output a selection signal. The first equalizer is coupled to the ADC, and configured to equalize the second digital signal to generate a third digital signal. The selector is coupled between the first equalizer, the ADC, and the clock data recovery circuit. The selector is configured to output the second digital signal or the third digital signal as the first digital signal according to the selection signal.

Communication receiving device and clock data recovery method

An analog-to-digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjusting circuitry. The ADC circuitries convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuitry performs at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuitry analyzes time difference information within even-numbered sampling periods of the clock signals, in order to generate adjustment signals. The adjustment signals are for reducing a clock skew in the ADC circuitries.

Analog-to-digital converter device and method for calibrating clock skew

An analog to digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjustment circuitry. The ADC circuitries are configured to convert an input signal according to interleaved clock signals, in order to generate first quantization outputs. The calibration circuitry is configured to perform at least one calibration operation according to the first quantization outputs, in order to generate second quantization outputs. The skew adjustment circuitry is configured to determine maximum value signals, to which the second quantization outputs respectively correspond during a predetermined interval, and to average the maximum value signals to generate a reference signal, and to compare the reference signal with each of the maximum value signals to generate adjustment signals, in order to reduce a clock skew of the ADC circuitries.

Analog to digital converter device and method of calibrating clock skew

An eye diagram measurement device includes a first mapping circuitry, a count circuitry, a second mapping circuitry and a memory circuitry. The first mapping circuitry maps one of plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits. The counter circuitry performs a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits, to generate a plurality of count signals. The second mapping circuitry maps the count signals respectively to a plurality of eye diagram measurement signals corresponding to a present phase. The memory circuitry stores the eye diagram measurement signals in order to provide the eye diagram measurement signals to an external system for generating an eye diagram measurement result of the electronic device.

Eye diagram measurement device and eye diagram measurement method

A calibration method applicable for a SAR ADC comprising a capacitor array, comprises the following operations: Inputting an input signal to the SAR ADC, wherein the SAR ADC is configured to generate an output signal according to the input signal, and the output signal comprises multiple selected digital codes; calculating average code densities for multiple digital code groups, respectively, wherein the multiple digital code groups are determined by dividing the multiple selected digital codes, and each of the multiple digital code groups comprises one or more selected digital codes of the multiple selected digital codes; calibrating capacitance of a first under-correction capacitor element of the capacitor array according to the first comparison result.

Calibration method and related calibration system

A signal transmission device includes a transceiver circuitry and a control circuitry. The transceiver circuitry is configured to receive first device data from an external device through a channel. The control circuitry is configured to calculate a least one system parameter of the transceiver circuitry based on the first device data, second device data associated with the transceiver circuitry, and at least one requirement of a predetermined communication protocol, in order to link with the external device.

Signal transmission device and linking method thereof

A sampling phase adjustment device and an adjusting method thereof are disclosed. Sampling phase adjustment device includes feedback summer, adaptive equalizer unit, clock and data recovery (CDR) circuit, data slicer, error slicer, sample calculator unit and enable circuit. The adjusting method is as follows: the data slicer and error slicer receive a sum value generated from the feedback summer, and generate a data signal and an error signal, respectively. The adaptive equalizer unit provides an equalizing signal to the feedback summer and a reference signal to the error slicer. The sample calculator unit generates a sampling adjustment signal based on the data signal and error signal. The CDR circuit is configured to output and adjust a clock signal based on the sampling adjustment signal and data signal. The enable circuit enables the adaptive equalizer unit and the sample calculator unit alternatively.

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Hsinchu, Taiwan

Yu-Chu Chen