Samsung Display Co., Ltd.

Yu-Chol Kim

Jihye Kim

Jakyoung Jin

Jin-Wook Yang

Min-soo Choi

Jae-Hyeon Jeon

Seongoh Yeom

Kihyun Pyun

Ji Hye Kim

Sujin Lee

Donggyu Lee

Kyunho Kim

Junpyo Lee

Young Ha Sohn

Jongjae Lee

Keunoh Kang

Jeong-Hyun Kim

Minyoung Park

JiYe Lee

Yoonsik Park

Youngsuk Jung

Hyehyun Jeong

A display device comprises a display panel including a pixel, and a panel driver configured to receive input image data in a variable frame frequency in order to drive the display panel based on the input image data. A frame period for the display panel is divided into at least one scan period and at least one or more hold periods, and a time during which the pixel performs an anode initialization operation in each of the hold periods is longer than a time during which the pixel performs the anode initialization operation in the scan period.

Display device and pixel of a display device

A pixel of an OLED display device includes a first capacitor, a second capacitor, a first transistor configured to generate a driving current, a second transistor configured to transfer a data voltage to a first node, a third transistor configured to diode-connect the first transistor, a fourth transistor configured to transfer an initialization voltage to the second node, a fifth transistor configured to transfer a reference voltage to the first node, a sixth transistor configured to couple a drain of the first transistor and an anode of an organic light emitting diode, a seventh transistor configured to transfer the initialization voltage to the anode of the organic light emitting diode, an eighth transistor configured to transfer the initialization voltage to the drain of the first transistor, and the organic light emitting diode.

Pixel of an organic light emitting diode display device, and organic light emitting diode display device

An embodiment provides a display device including: a light emitting diode; a driving transistor configured to supply a current to the light emitting diode; a switching transistor having an input electrode connected to a data line; and a voltage transmitting capacitor disposed between an output electrode of the switching transistor and a gate electrode of the driving transistor, wherein a data voltage applied to the data line may be transmitted to the gate electrode of the driving transistor through the voltage transmitting capacitor, and the data voltage may have a data voltage value from which a voltage variation variable is removed based on leakage of the switching transistor.

Display device and driving method of the display device

A display device includes a display panel including a pixel, a voltage line supplying a power voltage to the pixel, and a reference voltage line supplying one of a reference voltage and the power voltage to the pixel; a mode selector configured to output one of a first selection signal and a second selection signal according to an operation mode of the display panel; and a switch configured to provide the reference voltage or the power voltage to the reference voltage line in response to one of the first selection signal and the second selection signal.

Display device

A display apparatus includes a display panel, a gate driver and a data driver. The display panel displays an image. The gate driver outputs gate signals to the display panel. The data driver outputs data voltages to the display panel. The data driver includes a plurality of data driving circuits. At least two data driving circuits among the data driving circuits have different turn off timings or different turn on timings in a vertical blank period.

Display apparatus and method of driving display panel using the same

A display apparatus includes a gate driving control circuit, a gate driver and a display panel. The gate driving control circuit generates N gate clock signals and N inversion gate clock signals based on N gate clock control signals, phases of which partially overlap with each other. Each inversion gate clock signals has an opposite phase to a respective gate clock signal. The gate driver generates gate signals based on the N gate clock signals or the N inversion gate clock signals and applies the gate signals to gate lines. The display panel includes pixels, each connected to a respective gate line and a respective data line. Each of the pixels has a longer side in parallel with gate lines and a shorter side in parallel with the data lines. A number of the gate clock control signals is an integer multiple of a number of colors of the pixels.

Display apparatus and method of operating the same based on N gate clock control signals

A display device includes a display panel, and a power management circuit including a switching regulator for supplying a power in a discontinuous conduction mode or in a continuous conduction mode, and a sensing circuit for sensing whether the switching regulator is operated in the discontinuous conduction mode, the switching regulator including a comparator for monitoring the supplied power, and an RS latch for receiving an output signal from the comparator, and the sensing circuit including a phase lock loop circuit for generating a first clock signal, a phase delay circuit for generating a second clock signal having a phase delayed from the first, and a determination circuit for outputting a first value when a pulse width of the output signal from the RS latch is small, and for outputting a second value when the pulse width of the output signal from the RS latch is not small.

Power management circuit and display device having the same

A clock generation circuit includes: a clock generator to receive a gate pulse signal and to generate at least one gate clock signal corresponding to the gate pulse signal; an over-current protector to detect a current level of the at least one gate clock signal, and to output a shutdown enable signal and at least one switching signal corresponding to the detected current level; and a switching unit including at least one switching device to output the gate pulse signal as the at least one gate clock signal. The clock generator is to generate the at least one gate clock signal in response to the shutdown enable signal, and the at least one switching device is to transmit the gate pulse signal as the at least one gate clock signal in response to the at least one switching signal.

Growing community of inventors

Pyeongtaek-si, South Korea

Yu-Chol Kim