Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Yu-Ching Chang

Chien-Chih Chou

Chia-Der Chang

Cheng-Tao Wu

Yio-Wha Shau

Yu-Yu Lin

Bai-Kuang Hwang

Yi-Tung Yen

Chung-Cheng Liu

Shiu-Chieh Lan

Arvin Huang-Te Li

Chih-Ming Chen

Kuo-Yen Liu

Wen-Chen Chien

Wei-Cheng Lee

Jiun-Pyng You

Chun-Hu Ge

Chieh-Chih Chou

Yu-Da Fan

Min Shih

Wei-Sheng Lai

A time domain signal analysis method is provided. The signal analysis method includes the following steps. A signal to be analyzed is received. The signal to be analyzed is iteratively sifted by using Empirical Mode Decomposition (EMD) to extract at least one intrinsic function (IMF). A normalized Hilbert transform is performed on the IMF. The transformed IMF includes phase information. The transformed IMF is processed by means of phase processing to obtain the processed IMF including angular frequency information. The foregoing signal analysis method could be utilized in an ultrasound imaging system to identify image information of ultrasound images.

Signal and image analysis method and ultrasound imaging system

An image processing method is provided. The image processing method includes the following steps. A plurality of raw signal is received by a signal transceiving module of the ultrasound imaging system. It is determined whether each of the raw signals satisfies any condition in a condition group, and the raw signal satisfying any condition in the condition group is mapped to one of a plurality of preset constants to generate a plurality of first data. The raw signals not satisfying any condition in the condition group are processed according to a calculation formula to generate a plurality of second data. A beamforming procedure is simultaneously performed on the first and second data to obtain a beamformed image. The beamformed image is transformed to obtain an image of a region to be detected. Furthermore, an imaging system using the foregoing image processing method is also provided.

Imaging system and image processing method thereof

Disclosed are methods of identifying microRNA motifs or microRNA precursors for a target gene or a set of target genes. Also disclosed are related computer-readable media.

MicroRNA precursors

MicroRNA motifs

A semiconductor device includes a semiconducting substrate having CMOS transistors thereon. A composite etch stop layer including a lowermost silicon oxynitride portion and an uppermost silicon nitride portion is disposed on the semiconducting substrate including the CMOS transistors. At least one dielectric layer is on the composite etch stop layer. A first contact opening extends to a first level through the composite etch stop layer thickness and a second contact opening extends to a second level deeper than the first level through the composite etch stop layer.

Method for forming an improved low power SRAM contact

A method of forming contact openings in a semiconductor device including providing a semiconducting substrate; forming an etch stop layer on said semiconducting substrate; forming a dielectric layer on said etch stop layer; forming a bottom anti-reflective coating (BARC) on said dielectric layer; forming and patterning a mask on said BARC layer; and, forming at least a first contact opening exposing said etch stop layer by a first etching process.

Within a method for forming a microelectronic fabrication there is provided a substrate having formed thereover a patterned dielectric layer which defines a via. There is also formed within a lower portion of the via a tungsten stud layer having a recess thereabove within the via. There is also formed within the recess a patterned conductor capping layer formed of a conductor material other than tungsten. The patterned conductor capping layer may seal a void formed within the tungsten stud layer.

Tungsten plug with conductor capping layer

A fuse structure and method for fabricating same are disclosed. The fuse structure is designed for opening by conventional laser energy application. The fuse structure is characterized by an absence of high stress areas in the surrounding substrate thereby resulting in higher fabrication yields due to lower occurrence of substrate fracturing or other damage occasioned by the opening of the fuse.

Low stress integrated circuit fusible link

A method to provide low dielectric constant voids between adjacent conducting lines in a semiconductor device. Narrowly spaced metal lines are formed on the substrate surface. A dielectric layer is deposited overlying the metal lines and the substrate surface. A high water content, water saturated, environment is created for the spin-on-glass process. A pseudo-water condition exists on the surface of the dielectric layer prior to the deposition of the spin-on-glass layer. The spin-on-glass layer is deposited overlying the dielectric layer. Voids form in the spin-on-glass layer between the narrowly spaced metal lines. The spin-on-glass layer is baked. The integrated circuit device is completed.

Growing community of inventors

Hsinchu, Taiwan

Yu-Ching Chang