Macronix International Co., Ltd.

Yu-Chin Chien

Ching-Lin Chan

Cheng-Chi Lin

A semiconductor device is provided. The semiconductor device includes a first doped region and a second doped region of a first conductive type and a third doped region of a second conductive type located in a substrate. The second doped region is located at a side of the first doped region. A top-view pattern of the second doped region has at least one recess portion. The third doped region is located between the first doped region and the second doped region. A top-view pattern of the third doped region has at least one protruded portion corresponding to the at least one recess portion.

Semiconductor device

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a drift region formed in the high-voltage well, a drain region formed in the high-voltage well and spaced apart from the drift region, and a buried region having the first conductivity type formed in the high-voltage well between the drift region and the drain region.

Semiconductor device having buried region and method of fabricating same

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a high-voltage doped region having the first conductivity type and disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the high-voltage doped region, a source region disposed in the high-voltage doped region, a first gate structure disposed above a first side portion of the high-voltage doped region between the source region and the drain region, and a second gate structure disposed above a second and opposite side portion of the high-voltage doped region.

Semiconductor device having gate structures and manufacturing method thereof

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a source well having the first conductivity type and formed in the high-voltage well, a source region formed in the source well, an isolation layer formed above the high-voltage well and spaced apart from the source well, a gate layer formed above the substrate and continuously extending from above an edge portion of the source well to an edge portion of the isolation layer, and a metal layer formed above the substrate and the isolation layer. The metal layer includes a first metal portion overlapping an edge portion of the gate layer and a side portion of the isolation layer, a second metal portion overlapping and conductively contacting the gate layer, and a third metal portion overlapping and conductively contacting the source region.

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Taipei, Taiwan

Yu-Chin Chien