Silicon Motion, Inc.

Yu-Chih Lin

Chang-Kai Cheng

Yen-Hung Lin

Chia-Chien Wu

Po-Chia Chu

Chang-Wei Shen

Guan-Yao Huang

A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

Method and apparatus for performing access management of memory device in host performance booster architecture with aid of device side table information encoding and decoding

A method and associated apparatus for performing access management of a memory device with aid of dedicated bit information are provided. The method includes: transmitting a compact hybrid table comprising multiple compressed tables to a host device, for being stored in the host device, to allow the host device to send one of multiple compact hybrid table entries of the compact hybrid table to the memory device as reading reference; determining a starting logical address and a data length according to a read command packet from the host device, and determining a first mapping relationship and the dedicated bit information according to the read command packet; determining second mapping relationship(s) according to the first mapping relationship and the dedicated bit information; and reading the data from the NV memory for the host device at least according to the first mapping relationship and the second mapping relationship(s).

Method and apparatus for performing access management of a memory device with aid of dedicated bit information

The present invention provides a method for accessing a flash memory module, wherein the flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, each clock includes a plurality of pages, and the method includes the steps of: providing a read-retry table, wherein the read-retry table includes a plurality of read setting levels, each read setting level corresponds to at least one read voltage, and no two read setting levels have the same read voltage; establishing a read success recording table, which records at least one specific read setting level that was previously used to successfully read the flash memory module; and when it is required to the read the flash memory module, using the at least one specific read setting level recorded in the read success recording table to read the flash memory module.

Method for accessing flash memory module, associated flash memory controller and electronic device for accelerating reading speed of flash

The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, the flash memory module includes a plurality of flash memory chips, the flash memory controller includes a buffer memory and a microcontroller, and the buffer memory is arranged to store an in-system programming (ISP) code. When the flash memory controller enters a power saving mode, the microcontroller disables a portion of the buffer memory to make at least one portion of the ISP code disappear; and when the flash memory controller enters a normal mode from the power saving mode, the microcontroller reads said at least one portion of the ISP code from N flash memory chips within the plurality of flash memory chips, wherein N is a positive integer greater than one.

Flash memory controller, control method of flash memory controller and associated electronic device

A data storage device includes a flash memory and a controller. The flash memory is utilized to store at least one data. The controller is coupled to the flash memory to receive at least one read command transmitted from a host, and reads the data stored by the flash memory according to the read command. The controller determines whether or not the length of the read command is greater than a first predetermined value. If the length is greater than the first predetermined value, the controller arranges the read command on a sequential queue. If the length is not greater than the first predetermined value, the controller arranges the read command on a random queue. The controller executes the read command of the random queue at high priority.

Data storage method for optimizing data storage device and its data storage device

A memory device is provided. A processor accesses non-volatile memories via channels and generates a status table according to at least one command of a command queue. The status table records a plurality of tasks. Each task corresponds to one read status and one channel number. The processor selects a plurality of specific tasks from the tasks to serve as a first task set and simultaneously performs all the selected specific tasks with different channel numbers. When the read status of a first specific task matches a first predetermined status, the processor retrieves a logical-to-physical address mapping table relating to the logical address of the first specific task. When the read status of the first specific task matches a second predetermined status, the processor retrieves data relating to the logical address of the first specific task.

Memory device and data read method thereof

The present invention provides a data storage device including a flash memory, a random access memory, and a controller. The controller selects a first read command where the required mapping table has already been loaded on the random access memory from a plurality of read commands. Before a first read task prepared by the first read command is executed, the controller selects a second read command from the remaining read commands, selectively reads a first data sector of the first read command and the mapping table of the second read command at the same time, or reads the first data sector and a second data sector of the second read command at the same time.

Data storage device and data reading method thereof

In one implementation, an electronic system includes a host and a data storage device. The data storage device includes a flash memory, a controller and a delay circuit. The controller is configured to receive a read command from the host, read a first data sector from the flash memory according to the read command, and produce a setting signal according to a maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit is configured to receive the setting signal from the controller, divide the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmit at least one of the first sub-data sectors to the host at a predetermined time interval for extending a busy time of the controller.

Electronic system and data maintenance method thereof

The present invention provides a data storage device including a flash memory, a controller and a delay circuit. The controller receives a read command from a host, reads a first data sector from the flash memory according to the read command, and produces a setting signal according to the maintenance time of the flash memory when the flash memory needs to be maintained. The delay circuit receives the setting signal from the controller, divides the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmits at least one of the first sub-data sectors to the host at a predetermined time interval for extending the busy time of the controller.

Data storage device and data maintenance method thereof

A data storage device using a FLASH memory with replay-protected blocks. The storage space of the FLASH memory is divided into blocks and each block is further divided into pages. A controller is provided in the data storage device to couple to the FLASH memory. The controller manages at least one replay-protected memory block of the FLASH memory. The controller programs two pages into the at least one replay-protected memory block and each page is programmed with a write count of the at least one replay-protected memory block.

Data storage device and flash memory control method

A garbage collection method for a flash memory is provided. The flash memory includes a spare block pool and a data block pool, wherein the spare block pool includes spare blocks and the data block pool includes data blocks. The method includes the steps of: receiving target data from a host and writing the target data to a current data block of the data blocks; sorting an erase count of each data block when performing a wear-leveling process to write the target data; sorting a valid page number of each first block when it is determined that at least two first blocks in the data blocks have the smallest erase count; and selecting a second block having a smallest valid page number from the first blocks and writing valid pages of the second block to one of the spare blocks to perform a data cleaning process.

Garbage collection method for flash memory

A data storage device using a FLASH memory with replay-protected blocks. The storage space of the FLASH memory is divided into blocks and each block is further divided into pages. A controller is provided in the data storage device to couple to the FLASH memory. The controller manages at least one replay-protected memory block of the FLASH memory. The controller programs a success flag and a write count into a system block of the FLASH memory after the controller programs two pages into the at least one replay-protected memory block of the FLASH memory. The controller may perform a power restoration process based on the success flag of the system block or/and based on the amount of programmed pages of the at least one replay-protected memory block.

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Zhubei, Taiwan

Yu-Chih Lin