United Microelectronics Corp.

Yu-Chih Chuang

Min-Hung Wang

Tsong-Lin Shen

Sheng-Wei Hung

Chin-Tsai Chang

Chien-Chung Su

Chih-Cheng Wang

Cheng-Chih Kung

Tse-Yi Lu

Yi-Min Jen

Nai-Jen Yeh

Che-Pin Tseng

Hai-Hung Wen

A method for fabricating a semiconductor device is disclosed. A semiconductor substrate comprising a MOS transistor is provided. A MEMS device is formed over the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.

Method for fabricating MEMS device integrated with a semiconductor integrated circuit

A semiconductor device includes a semiconductor substrate comprising a MOS transistor. A MEMS device is integrally constructed above the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.

MEMS device integrated with a semiconductor integrated circuit and manufacturing method thereof

A method of forming a composite silicon oxide layer over a semiconductor device. The composite silicon oxide layer is formed between the semiconductor device and a doped silicate glass layer. The composite silicon oxide layer comprises two silicon oxide layers, each having a different silicon/oxide composition. The oxygen-rich oxide layer or silicon dioxide layer is formed directly above the semiconductor device, and the silicon-rich oxide layer is formed above the silicon dioxide layer next to the doped silicate glass layer. Both the silicon dioxide layer and the silicon-rich oxide layer are formed in the same plasma deposition chamber.

Method of forming composite silicon oxide layer over a semiconductor device

A method of fabricating a buried contact in a static random access memory. A gate oxide layer, a first conducting layer and a masking layer are formed sequentially on a substrate. A buried contact opening is formed inside the gate oxide layer, the first conducting layer and the masking layer, which opening exposes a part of the substrate. An epitaxial layer is formed inside the buried contact opening, which epitaxial layer fills up the buried contact opening. After the masking layer is removed, a second conducting layer is formed above the substrate. A buried contact is formed in the substrate that is below the epitaxial layer. The gate oxide layer, the first conducting layer, the epitaxial layer and second conducting layer are patterned to expose a part of the substrate and a part of the buried contact. A source/drain is formed in the substrate and a part of the source/drain is mixed with a part of the buried contact.

Method of fabricating a static random access memory

Although the spacers are formed on the sidewalls of gate electrode and words lines via the same steps of deposition and etch-back processes, only the spacers disposed at the sidewalls of the gate electrode are practical for fabricating peripheral devices with LDD structure, and such fabrication is impractical in the memory cell region. On the contrary, the region beneath the spacers disposed at the sidewalls of word lines will become the path through which leakage current flows. The present invention makes use a shielding layer to cover the second active region as a masking, and then removes the spacers disposed at the sidewalls of word lines. Afterwards, isolating regions are formed through one implantation procedure to thereby decrease leakage current and simplify the process flow.

Growing community of inventors

Tainan, Taiwan

Yu-Chih Chuang