United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Yu-Chieh Lin

Li-Wei Feng

Chien-Ting Ho

Ying-Chiao Wang

Tsung-Ying Tsai

Shih-Fang Tzou

Chun-Yuan Wu

Ming-Te Wei

Chin-Fu Lin

Chun-Hung Cheng

Yau-Kae Sheu

Liang-An Huang

Yuan-Cheng Yang

Yu-Chun Huang

Hsin-Liang Liu

Yu-Ciao Lin

A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.

Method for patterning a semiconductor structure

A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.

Semiconductor device and method of manufacturing a semiconductor device

An etching method including the following steps is provided. A substrate is provided first. A first region and a second region adjacent to the first region are defined on the substrate. A material layer is formed on the substrate. A pattern mask is formed on the material layer. The patterned mask includes a first part covering the material layer on the first region and a second part including a lattice structure. The lattice structure includes a plurality of openings and a plurality of shielding parts. Each opening exposes a part of the material layer on the second region. Each shielding part is located between the openings adjacent to one another. Each shielding part covers a part of the material layer on the second region. An isotropic etching process is then performed to remove the material layer exposed by the openings and the material layer covered by the shielding parts.

Etching method

The present invention proposes a method of manufacturing a semiconductor device, which includes the steps of providing a substrate with a memory region and a logic region, forming bit lines and logic gates respectively in the memory region and the logic region, wherein storage node regions are defined between bit lines, forming a first low-K dielectric layer on sidewalls of bit lines, forming a doped silicon layer in the storage node regions between bit lines, wherein the top surface of doped silicon layer is lower than the top surface of bit line, forming a second low-K dielectric layer on sidewalls of storage node regions, and filling up storage node regions with metal plugs.

Method of manufacturing a semiconductor device

A method for forming a semiconductor device includes providing a substrate having a plurality of memory cells formed therein; forming an insulating layer on the substrate; forming a plurality of openings in the insulating layer and exposing a portion of the memory cells; forming a conductive portion and a metal layer in the openings; removing a portion of the metal layer to form a plurality of first metal portions and a plurality of second metal portions that the first metal portion and the conductive portion form a first connecting structure, and the second metal portion and the conductive portion form a second connecting structure; forming a passivation layer on the first connecting structures; and forming a plurality of first storage nodes and dummy nodes on the substrate and the first storage nodes and the dummy nodes are electrically connected to the second connecting structures and the first connecting structures respectively.

Method for forming semiconductor device

A semiconductor device include a substrate including at least a memory cell region formed thereon, an isolation mesh formed on the substrate; and a plurality of storage node contact plugs. The semiconductor device includes a plurality of memory cells formed in the memory cell region. The isolation mesh includes a plurality of essentially homogeneous dielectric sidewalls and a plurality of first apertures defined by the dielectric sidewalls. The storage node contact plugs are respectively formed in the first apertures, and electrically connected to the memory cells respectively.

Semiconductor device and method for forming the same

A semiconductor device includes a substrate including at least a memory region defined therein and a plurality of memory cells formed in the memory region, a plurality of first connecting structures, a plurality of second connecting structures, a plurality of dummy nodes respectively disposed on the first connecting structures, and a plurality of first storage nodes respectively disposed on the second connecting structures. The first connecting structures respectively include a conductive portion and a first metal portion, and the second connecting structures respectively include the conductive portion and a second metal portion. The first metal portion and the second metal portion include the same material. And the first metal portion and the second metal portion include different heights.

A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.

Growing community of inventors

Kaohsiung, Taiwan

Yu-Chieh Lin