Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Chia Liang

Yen-Ming Chen

Feng-Cheng Yang

Shih-Hao Lin

Kuo-Feng Yu

Jian-Hao Chen

Hui-Chi Chen

Chia-Wei Chen

Kuei-Lun Lin

Shan-Mei Liao

Chih-Yu Hsu

Chung-Liang Cheng

Hsiang-Pi Chang

Pinyen Lin

Huang-Lin Chao

Chansyun David Yang

Tzer-Min Shen

Yao-Sheng Huang

Chun-I Wu

Wen-Chung Liu

Yen-Tien Tung

Duen-Huei Hou

Shen-Yang Lee

Chun-Chun Lin

A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The semiconductor device includes a first gate structure and a second gate structure. The first gate structure includes a first interfacial oxide (IO) layer, a first high-K (HK) dielectric layer disposed on the first interfacial oxide layer, and a first dipole layer disposed at an interface between the first IL layer and the first HK dielectric layer. The HK dielectric layer includes a rare-earth metal dopant or an alkali metal dopant. The second gate structure includes a second IL layer, a second HK dielectric layer disposed on the second IL layer, and a second dipole layer disposed at an interface between the second IL layer and the second HK dielectric layer. The second HK dielectric layer includes a transition metal dopant and the rare-earth metal dopant or the alkali metal dopant.

Gate structures in semiconductor devices

A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.

Semiconductor device with tunable threshold voltage and method for manufacturing the same

A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Multi-layer high-k gate dielectric structure

Growing community of inventors

Hsinchu, Taiwan

Yu-Chia Liang