Lucent Technologies Inc.

Agere Systems Inc.

Yu-Chi Wang

Jenn-Ming Kuo

Keith Wayne Goossen

Rose Fasano Kopf

Minghwei Hong

Robert Alan Hamm

Jueinai Raynien Kwo

Robert William Ryan

Joseph Petrus Mannaerts

Alaric Tate

A method of fabricating a III-V heterostructure semiconductor device. The method includes the steps of forming at least one conductive post overlying a semiconductor region to form a structure, encapsulating the structure and the conductive post to form a planarized cured passivation layer, and exposing the conductive post through the planarized cured passivation layer to form the semiconductor device.

Method of fabricating a heterojunction bipolar transistor

A novel method of forming a GaAs-based MOS structure comprises ion implantation after oxide formation, and subsequent slow heating and cooling, carried out such that essentially no interfacial defects that are detectable by high resolution transmission electron microscopy are formed. If the MOS structure is a MOS-FET then metal contacts are provided in conventional fashion. A post-metallization anneal can result in FETs that are substantially free of drain current/voltage hysteresis. MOS-FETs made according to the novel method can be produced with high yield and can have significantly increased lifetime, as compared to some prior art GaAs-based MOS-FETs.

Method of making an article comprising an oxide layer on a GaAs-based semiconductor body

In a method of making a flip-chip bonded GaAs-based opto-electronic device, removal of the GaAs substrate is facilitated by provision of a lattice matched (Al.sub.x Ga.sub.1-x)InP etch stop layer, exemplarily a Ga.sub.0.51 In.sub.0.49 P layer, and use of an etchant that isotropically etches GaAs such that an essentially mirror-like etch stop layer surface results, and that preferably exhibits an etch rate ratio of at least 200:1 for GaAs and the etch stop layer, respectively. Use of the novel substrate removal method can substantially increase device yield, and facilitate manufacture of large device arrays, e.g., arrays of detector/modulator diodes flip-chip bonded to Si CMOS chips.

Method of making a flip-chip bonded GaAs-based opto-electronic device

In a DH-PHEMT the channel layer comprises InGaAs and the donor layers comprise In.sub.0.5-q (Al.sub.x Ga.sub.1-x).sub.0.5+q P in which the mole fraction of Al is in the range of about 0.2.ltoreq.x.ltoreq.0.3. In another embodiment, an InAlGaP layer forms a Schottky barrier gate contact with a barrier height of about 1.0 eV and hence low leakage current. The devices exhibit high 2DEG density, current drivability, and breakdown voltage, making them suitable for low voltage application such as battery-powered, portable wireless equipment. The Schottky barrier contact may be used in devices other than HEMTs.

InAlGaP devices

In a DH-PHEMT the channel layer comprises InGaAs, the donor layers comprise In.sub.y Ga.sub.1-y P(0.15.ltoreq.y.ltoreq.0.85), and each of the spacer layers comprises an In.sub.0.5-q (Al.sub.x Ga.sub.1-x).sub.0.5+q P outer spacer layer (0.2.ltoreq.x) and an Al.sub.r Ga.sub.1-r As (0.ltoreq.r.ltoreq.0.3) inner spacer layer. In another embodiment, a similar InAlGaP layer forms a Schottky barrier gate contact with a barrier height of at least 1.0 eV and hence low leakage current. The devices exhibit the capability for both low noise and high power operation at low supply voltages.

Growing community of inventors

Piscataway, NJ, United States of America

Yu-Chi Wang