Gsi Technology, Inc.

Yu-Chi Cheng

Patrick Chuang

Jae-Hyeong Kim

A system, method and circuits are described that pertain to locked loop circuits, distributed duty cycle correction loop circuitry. In some embodiments, the system and circuit may involve or be configured for coupling with lock loop circuitry such as phase locked loop (PLL) circuitry and/or a delay locked loop (DLL) circuitry. For example, one illustrative implementation may include or involve a phase locked loop (PLL) with distributed duty cycle correction loop/circuitry.

Systems and methods involving lock loop circuits, distributed duty cycle correction loop circuitry

Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry

Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features

Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.

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San Ramon, CA, United States of America

Yu-Chi Cheng