Fujian Jinhua Integrated Circuit Co., Ltd.

Yu-Cheng Tung

Janbo Zhang

Yi-Wang Jhan

Yifei Yan

Xiaopei Fang

Gang-Yi Lin

Li-Wei Feng

Ken-Li Chen

Chia-Wei Wu

Tsung-Wen Chen

Huixian Lai

Chao-Wei Lin

Min-Teng Chen

Tsuo-Wen Lu

Chia-Yi Chu

Guoguo Kong

Meng Qi Zhuang

Pei-Ting Tsai

Fu-Che Lee

An-Chi Liu

Yi-Lei Tseng

Yung-Tai Huang

Shaoyi Wu

Xin You

The present disclosure provides a semiconductor device and a fabricating method thereof, including a substrate, a supporting structure and a capacitor structure. The supporting structure is disposed on the substrate, and the supporting structure includes a first supporting layer and a second supporting layer. The capacitor structure is disposed on the substrate and includes a plurality of bottom electrode layers. Each of the bottom electrode layers includes two portions extended upwardly, and one of the two portions has a first thickness between the substrate and the first supporting layer, and a second thickness between the first supporting layer and the second supporting layer, and the first thickness is greater than the second thickness.

Semiconductor device and method of fabricating the same

The present disclosure provides a three-dimensional memory device and a method of fabricating the same, which includes a substrate, and a memory stack structure. The memory stack structure is disposed on the substrate, and includes a plurality of stack units sequentially stacked into a staircase shape, wherein each of the stack units has a stepped slope, the stepped slope of any one of the stack units disposed in a related lower position is less than the stepped slope of another one of the stack units disposed over the one of the stack units. Through this arrangements, the three-dimensional memory device may therefore obtain an optimized structural integrity, as well as improved component efficiency.

Three-dimensional memory device and method for fabricating the same

The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device includes a substrate, a capacitor structure, a sidewall high-k dielectric layer and a supporting structure. The capacitor structure is disposed on the substrate, and includes a plurality of columnar bottom electrodes, a capacitor dielectric layer and a top electrode layer, wherein each of the columnar bottom electrodes includes a recess on the top. The sidewall high-k dielectric layer is disposed on two opposite sidewalls of each of the columnar bottom electrodes, wherein a portion of the capacitor dielectric layer is filled in the recess and sandwiched between the columnar bottom electrodes and the sidewalls high-k dielectric layer. The supporting structure is disposed between the adjacent ones of the columnar bottom electrodes, and includes a first supporting layer and a second supporting layer stacked from bottom to top.

Semiconductor device and fabricating method thereof

The present disclosure relates to a semiconductor memory device and a fabricating method thereof, includes a substrate, a plurality of gate structures, a plurality of isolation fins, at least one bit line, and a plug. The gate structures are disposed in the substrate, being parallel with each other along a first direction. The isolation fins are disposed on the substrate, parallel with each other and extending along the first direction, over each of the gate structures respectively. The bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The bit line includes a plurality of pins extending toward the substrate, being alternately arranged with the isolation fins along the second direction. The plug is disposed on the substrate, being alternately with the bit line in the first direction.

Semiconductor memory device comprises a bit line having a plurality of pins extending toward a substrate

A semiconductor device includes a substrate having a plurality of parallel active regions, an isolation structure in the substrate to separate the active regions, a buried word line disposed in the substrate and cutting through the isolation structure and the active regions, and a dielectric insert structure disposed in the substrate, directly under the buried word line and between end portions of adjacent two of the active regions. A bottom surface of the dielectric insert structure is lower than a bottom surface of the isolation structure.

Semiconductor device including dielectric insert structure directly under buried word line and method for forming the same

A semiconductor structure including a substrate, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer and in physical contact with the first dielectric layer, an opening on the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an conductive layer disposed on the second dielectric layer at two sides of the opening and in physical contact with the second dielectric layer, a contact structure disposed in the lower portion of the opening, and a passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the conductive layer.

Semiconductor structure and method for forming the same

The present disclosure provides a semiconductor device and a method of fabricating the same, and the semiconductor device includes a substrate, active areas, and an isolation structure. The active areas are parallel and separately disposed with each other in the substrate, and each of the active areas includes an active fin and active ends disposed at two sides of the active fin. The active fin and the active ends include different materials. The isolation structure is disposed in the substrate to surround the active areas. With this arrangement, the extending area of the active areas may be improved, so as to make sure the storage node contacts formed subsequently may directly and stably contact with the active areas.

A method for fabricating a semiconductor structure includes the following steps. Decomposing a layout to first connection patterns and second connection patterns alternatively arranged with each other, where a to-be-split pattern is disposed between the first connection pattern and the second connection pattern; splitting the to-be-split pattern into a cutting portion and a counterpart cutting portion; forming a first photomask having a layout constructed by the first connection pattern and the cutting portion; forming a second photomask having a layout constructed by the second connection pattern and the counterpart cutting portion; transferring layouts of the first and second photomasks to a target layer to form connection patterns and a merged pattern, where the contour of the merged pattern is defined by the cutting portion and the counterpart cutting portion, and each end surface of the merged pattern comprises a recessed region and a protruded region.

Semiconductor structure, method for fabricating thereof, and method for fabricating semiconductor layout

A semiconductor structure is provided in the present invention, including a substrate with multiple recesses and active areas, multiple bit lines spaced apart in a first direction on the cell region and extending in a second direction perpendicular to the first direction, and the bit line is electrically connected to an active area in the substrate through the recess, and a dummy bit line at an outermost side of the multiple bit lines in the first direction and extending in the second direction, wherein a width of the dummy bit line in the first direction is larger than a width of the bit line in the first direction, and the bit lines and the dummy bit line have the same composition and layer structures.

Semiconductor structure and method of manufacturing the same

The present disclosure provides a semiconductor memory device and a fabricating method thereof, which includes a substrate, a plurality of buried word lines, and a plurality of storage node contacts. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are embedded in the substrate, across the shallow trench isolation and the active areas. The storage node contacts directly contact the active areas and include a plurality of first plugs, with each first plug including an insulating material and a conductive material stacked sequentially from bottom to top. Within the semiconductor memory device, at least one active area simultaneously contacts two of the first plugs, or a storage node pad physically contacts at least two of the first plugs. Thus, the present disclosure is beneficial on forming the semiconductor memory device with better component reliability.

Semiconductor memory device and method of fabricating the same

A semiconductor memory device including an array region and a peripheral region surrounding the array region. The array region includes a plurality of active regions and a first insulating layer disposed between the active regions. The peripheral region includes a peripheral structure, a second insulating layer surrounding the peripheral structure, and a third insulating layer surrounding the second insulating layer. At least a buried word line extends through the array region and the peripheral region, wherein a portion of the buried word line through the second insulating layer comprises a neck profile from a plan view.

Semiconductor memory device having buried word line with a neck profile portion

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a plurality of gate conductive patterns on the substrate; an interlayer dielectric layer covering the gate conductive patterns on the substrate; an interconnect structure comprising a contact plug and a first contact pad, the contact plug extending through the interlayer dielectric layer to the substrate, the first contact pad fully covering a top of the contact plug and extending laterally over part of a top surface of the interlayer dielectric layer; and a second contact pad formed on the top surface of the interlayer dielectric layer and spaced apart from a side edge of the first contact pad, wherein the second contact pad is formed and fully overlays on the interlayer dielectric layer and an isolation plug is spaced apart from the first contact pad.

Semiconductor structure

The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.

A semiconductor device includes a substrate, a plurality of active regions disposed in the substrate and respectively extending along a first direction and arranged into an array, and a plurality of isolation structures disposed in the substrate between the active regions. The isolation structures respectively comprise an upper portion and a lower portion, wherein a sidewall of the upper portion comprises a first slope, a sidewall of the lower portion comprises a second slop, and the first slope and the second slope are different. The semiconductor device further includes a plurality of semiconductor layers disposed between the upper portions of the isolation structures and the active regions.

Semiconductor device having semiconductor layers disposed between upper portions of the isolation structures and the active regions

A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.

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Quanzhou, China

Yu-Cheng Tung