United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Winbond Electronics Corporation

Untied Microelectronics Corp.

Chunghwa Picture Tubes, Ltd.

United Microelectric Corp.

Yu-Cheng Tung

En-Chiuan Liou

Chih-Wei Yang

Feng-Yi Chang

Li-Wei Feng

Janbo Zhang

Fu-Che Lee

Chun-Lung Chen

Kun-Yuan Liao

An-Chi Liu

Xiang Li

Ming-Feng Kuo

Shih-Fang Tzou

Chia-Lin Lu

Chien-Ting Ho

Shao-Hui Wu

Chia-Chen Sun

Ssu-I Fu

Chun-Hsien Lin

Chih-Sen Huang

Sheng-Yuan Hsueh

Shui-Yen Lu

Ying-Chiao Wang

Ding-Lung Chen

Gang-Yi Lin

Jhen-Cyuan Li

Hon-Huei Liu

Hsien-Shih Chu

Rung-Yuan Lee

Yu-Ming Lin

Chien-Ting Lin

Shih-Hung Tsai

Chin-Fu Lin

Wai-Yi Lien

Chun-Yuan Wu

Cheng-Tung Huang

Chih-Wei Chen

Ming-Jui Chen

Chao-Hung Lin

Su Xing

Chia-Wei Huang

Chung-Fu Chang

Po-Wen Su

Chin-Sheng Yang

Ming-Tsung Chen

Hsiao-Pang Chou

Wen-Tai Chiang

Ji-Fu Kung

Jen-Yu Wang

Ying-Tsung Chen

Man-Ling Lu

Li-Chiang Chen

Sho-Shen Lee

Hsin-Ming Hou

Feng-Ming Huang

Huixian Lai

Tsung-Wen Chen

Ming-Chang Lu

Hsueh-Wen Wang

Tan-Ya Yin

Yi-Wei Chen

Ching-Wen Hung

Chih-Kai Hsu

Yu-Hsiang Hung

Jyh-Shyang Jenq

Chia-Hung Lin

Shen-De Wang

Chih-Sheng Chang

Yu-Tsung Lai

Zhibiao Zhou

Tsuo-Wen Lu

Chin-I Liao

Chien-Hao Chen

Yen-Liang Wu

Ching-Ling Lin

Liang Yi

Chun-Tsen Lu

Wei-Hao Huang

Chia-Lung Chang

Wei-Hsin Liu

Ying-Chih Lin

Chun-Chi Yu

Ching-Li Yang

Chih-Chien Chang

Chia-Hung Wang

Kao-Tsair Tsai

Ming-Shing Chen

Chien-Cheng Tsai

Yifei Yan

Yuan-Chi Pai

Po-Chun Chen

Chia-Hsun Tseng

Kuan-Hung Chen

Weichang Liu

Yi-Wang Zhan

Yuan-Hsiang Chang

Chia-Liang Liao

Jianjun Yang

Chia-Yi Chu

Hai Biao Yao

A DRAM includes a substrate, a plurality of first active regions disposed on the substrate and arranged end-to-end along the first direction, and a plurality of second active regions disposed between the first active regions and arranged end-to-end along the first direction. The second active regions respectively have a first sidewall adjacent to a first trench between the second active region and one of the first active regions and a second sidewall adjacent to a second trench between the ends of the first active regions, wherein the second sidewall is taper than the first sidewall in a cross-sectional view.

Dynamic random access memory device with active regions of different profile roughness and method for forming the same

The present disclosure relates to a semiconductor device and a method of fabricating the same, the semiconductor device including a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate, including a plurality of first active fragments and a plurality of second active fragments. The first active fragments and the second active fragments are parallel and separately extended along a first direction, and the second active fragments are disposed outside all of the first active fragments. The first active fragments have a same length in the first direction, being a first length, the second active fragment have a second length in the first direction, and the second length is greater than the first length.

Semiconductor device and method of fabricating the same having a second active region disposed at an outer side of a first active region

The present disclosure relates to a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruded from the substrate. The gate line is disposed over the substrate, across the first fins, to further include a gate electrode and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on lateral surfaces of the first fins and on a top surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.

Semiconductor device and method of forming the same

The present disclosure relates to a semiconductor device and a method of fabricating the same, which includes a substrate, a plurality of bit lines, a plurality of first plugs, a first spacer, a second spacer, a plurality of second plugs and a metal silicide layer. The bit lines are disposed on the substrate. The first plugs are disposed on the substrate and separated from the bit lines. The first spacer and the second spacer are disposed between each of the bit lines and the first plugs, and include a first height and a second height respectively. The second plugs are disposed on the first plugs respectively, and the metal silicide layer is disposed between the first plugs and the second plugs, wherein an end surface of the metal silicide layer is clamped between the second spacer and the first spacer.

Semiconductor device and method of fabricating the same

The invention discloses a semiconductor memory device, which is characterized by comprising a substrate defining a cell region and an adjacent periphery region, a plurality of bit lines are arranged on the substrate and arranged along a first direction, each bit line comprises a conductive part, and the bit line comprises four sidewalls, and a spacer surrounds the four sidewalls of the bit line, the spacer comprises two short spacers covering two ends of the conductive part, two long spacers covering the two long sides of the conductive part, and a plurality of storage node contact isolations located between any two adjacent bit lines, at least a part of the storage node contact isolations cover directly above the spacers. The structure of the invention can improve the electrical isolation effect, preferably avoid leakage current and improve the quality of components.

Semiconductor memory device

A semiconductor structure includes a substrate comprising a peripheral region and a memory region defined thereon, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer, an opening on the peripheral region of the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an interconnecting structure disposed on the second dielectric layer and two sides of the opening, a contact structure disposed in the lower portion of the opening, and a spacer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the interconnecting structure.

Semiconductor structure and method for forming the same

A semiconductor memory device includes a substrate, at least one word line, a plurality of bit lines and a plurality of insulating structures. The word line is disposed in the substrate, extends along a first direction, and includes a gate cap layer. The bit lines are disposed on the substrate and respectively extend along a second direction. The bit line crosses the word line, and includes a conductive layer. The insulating structures are disposed on the word line and respectively disposed between the bit lines. The bottom surface of the insulating structure is located in the gate cap layer. The area of the top surface of the insulating structure is larger than the area of the bottom surface of the insulating structure.

A semiconductor structure includes a substrate having first and second bottom electrodes disposed thereon. The first bottom electrode includes a first sidewall and a second sidewall. An upper portion of the first sidewall comprises a slope profile. The second bottom electrode includes a third sidewall and a fourth sidewall. The second sidewall is opposite to the third sidewall. An upper supporting layer extends laterally between and the first bottom electrode and the second bottom electrode and directly contacts the second sidewall and the third sidewall. A lower end of the slope profile is not lower than a lower surface of the upper supporting layer. A cavity extends laterally between the substrate and the upper supporting layer. A capacitor dielectric layer is formed along the first bottom electrode and the second bottom electrode. A conductive material is formed on the capacitor dielectric layer and fills the cavity.

Semiconductor structure including capacitor and method for forming the same

A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.

The present invention discloses a semiconductor memory device, including a substrate, active areas, first wires and at least one first plug. The active areas extend parallel to each other along a first direction, and the first wires cross over the active areas, wherein each of the first wires has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first wire and electrically connected with the first wire, wherein the first plug entirely wraps the first end of the first wire and is in direct contact with a top surface, sidewalls and an end surface of the first end. Therefore, the contact area between the plug and the first wires may be increased, the contact resistance of the plug may be reduced, and the reliability of electrical connection between the plug and the first wires may be improved.

A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.

Memory device and fabrication method thereof

The present disclosure relates to a semiconductor device and a fabricating method thereof, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Semiconductor device having bit line comprising a plurality of pins extending toward the substrate

A semiconductor device includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.

Semiconductor device

The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.

Method of fabricating semiconductor memory having a second active region disposed at an outer side of a first active region

A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Semiconductor structure and method of forming same

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Kaohsiung, Taiwan

Yu-Cheng Tung