Realtek Semiconductor Inc.

Yu-cheng Lo

Ching-Feng Huang

Chun-Yi Kuo

Po-Lin Chen

The present disclosure discloses a multi-core processing circuit having power-stabilizing test mechanism that includes a plurality of core-processing circuits arranged in an order and a self-test scheduling circuit. Each of the core-processing circuits includes a memory built-in self-test circuit. The self-test scheduling circuit receives a main activation signal to activate the memory built-in self-test circuit of one of the core-processing circuits every delay time in the order based on signal handshake to perform self-test, wherein one of the activated core-processing circuits has a largest average power draining amount in a predetermined range within the delay time.

Multi-core processing circuit and test method of the same having power-stabilizing test mechanism

An electronic device and a method for performing clock gating in the electronic device are provided. The electronic device includes at least one function circuit, a device under test (DUT) circuit and at least one gating circuit. The function circuit is configured to operate according to at least one primary clock, and the DUT circuit is configured to operate according to at least one secondary clock. In addition, the clock gating circuit is configured to control whether to enable the primary clock according to at least one primary enable signal, and control whether to enable the secondary clock according to the primary enable signal and a secondary enable signal.

Electronic device and method for performing clock gating in electronic device

A system, comprising: a plurality of first latches; a compressor circuit, coupled to the first latches, configured to compress an first signal having X bits from the first latches to a second signal having Y bits, wherein X and Y are positive integers and X is larger than Y; and at least one second latch, coupled to the compressor circuit, configured to receive the second signal to generate a scan output, wherein each of the first latches and the second latch forms a D flip flop. The system outputs the first signal but none of the scan output in a normal mode, and outputs the scan output but none of the first signal in a test mode.

System and method which can reduce circuit area while performing test function

A testing circuitry includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit is configured to generate an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and generate a first control signal in response to the scan enable signal, a plurality of first bits, and the reference clock signal. The first clock adjustment circuit is configured to generate a first test clock signal according to the first control signal and the internal clock signal, in order to test a multicycle path circuit. The plurality of first bits are to set a first pulse of the first test clock signal, in order to prevent the multicycle path circuit from occurring a timing violation.

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HSINCHU, Taiwan

Yu-cheng Lo