Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Cheng Liu

Che-Cheng Chang

Chen-Hsiang Lu

Hung-Hao Chen

Wei-Ting Chen

Horng-Huei Tseng

Wen-Tung Chen

Jui-Ping Chuang

Yu-Shu Chen

Wei Ting Chen

Chih-Han Lin

Shih-Ping Hong

Yungtzu Chen

Shu-Huei Suen

Ying Zhang

Tien-Chih Cheng

Jian-Huah Chiou

A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

Removing polymer through treatment

A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Semiconductor device and method of manufacture

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

Structure of semiconductor device structure having fins

A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H). The method further includes controlling a flow rate of the hydrogen gas (H) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.

Method for forming semiconductor device structure with fine line pitch and fine end-to-end space

A semiconductor structure includes an etching stop layer over an inter-layer dielectric (ILD) layer; a low-k dielectric layer over the etching stop layer; and a tapered conductor extending through the low-k dielectric layer and the etching stop layer and partially through the ILD layer; wherein the tapered conductor includes a recess disposed within the ILD layer and indented towards the etching stop layer and the low-k dielectric layer, and a protrusion surrounding the recess and protruded from the etching stop layer towards the ILD layer.

Semiconductor structure with tapered conductor

A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

MIM capacitor with top electrode having footing profile and method forming same

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.

Growing community of inventors

Zhubei, Taiwan

Yu-Cheng Liu