Macronix International Co., Ltd.

Yu-Chen Wang

Kuen-Long Chang

Ken-Hui Chen

Chun-Hsiung Hung

Nai-Ping Kuo

Chia-Feng Cheng

Chin-Hung Chang

Su-Chueh Lo

Min-Hsiung Meng

A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.

Configurable security memory region

An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.

Memory device and erasing method thereof

An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.

Retention logic for non-volatile memory

A method and a system for operating a memory are provided. The memory includes a plurality of memory cells which are configured to store data. The method includes the following steps. A counting number recorded in a counter is counted by 1, if the memory is written. The memory is set as a frequently using device, if the counting number recoded in the counter reaches a predetermined value.

Method and system for operating memory

An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.

Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.

Method and apparatus for leakage suppression in flash memory in response to external commands

Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block.

Growing community of inventors

Kaohsiung, Taiwan

Yu-Chen Wang