Test Research, Inc.

Yu-Chen Shen

Jia-Yan Gao

Yi-Hao Hsu

Kuei-Chang Yang

A test signal transmission apparatus used in a multi-chassis test device is provided. The test signal transmission apparatus includes global buses and test signal transmission modules each including an I/O port coupled to a test controller, a test bus coupled to an in-circuit-tester system and a bridge matrix including an output unit and an input unit. The output unit either routes a first output signal from the I/O port to the test bus, or routes the first output signal to one of the global buses and routes a second output signal from another one of the global buses to the test bus. The input unit either routes a first input signal from the test bus to the I/O port, or routes the first input signal to one of the global buses and routes a second input signal from another one of the global buses to the I/O port.

Multi-chassis test device and test signal transmission apparatus of the same

A device for performing timing analysis used in a programmable logic array system is provided. The device comprises first and second basic I/O terminals, a channel multiplexer, high-speed I/O terminals, a sampling module and a timing analysis module. The first basic I/O terminals receive under-test signals from an under-test unit. The channel multiplexer receives the under-test signals from the first basic I/O terminals to select at least a group of the under-test signals to be outputted to the second basic I/O terminals. The high-speed I/O terminals has a logic level analyzing speed higher than that of the first and second basic I/O terminals. The sampling module receives the group of under-test signals from the high-speed I/O terminals and samples the group of under-test signals to generate a sample result. The timing analysis module performs timing analysis and measurement according to the sample result.

Device and method for performing timing analysis

A signal transition detection circuit is provided. The signal transition detection circuit comprises a counter module, a DAC, a comparator and a digital sampling module. The counter module generates a digital step signal. The DAC converts the digital step signal into an analog input signal and transmits it to an under-test circuit such that the under-test circuit generates an output signal transiting from a first stable level to a second stable level, wherein a transition section is located between the first and the second stable level. The comparator receives and compares the output signal with a default value to generate a normalized output signal. The digital sampling module samples the normalized output signal to retrieve impulses such that when the number of the impulses is accumulated to be larger than a reference value, a corresponding step of the digital step signal is determined to be a transition point.

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Taipei, Taiwan

Yu-Chen Shen